THS10064 Datasheet, PDF (28/41 Pages) Texas Instruments – 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
timing and signal description of the THS10064 (continued)
write timing (using WR, WR-controlled)
Figure 16 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only.
The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is
the last external signal of CS0, CS1, and WR which becomes valid.
CS0
CS1
tsu(CS)
tw(WR)
th(CS)
WR
10%
10%
RD^{ÎÎÎÎÎÎÎÎÎÎ}
ÏÏÏÏÏÏÏÏ
tsu
th
D(0–9)
90%
90%
DATA_AV ^{ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ}
Figure 16. Write Timing Diagram Using WR (WR-controlled)
write timing parameter using WR (WR-controlled)
PARAMETER
tsu(CS)
tsu
th
th(CS)
tw(WR)
Setup time, CS stable to last WR valid
Setup time, data valid to first WR invalid
Hold time, WR invalid to data invalid
Hold time, WR invalid to CS change
Pulse duration, WR active
MIN TYP MAX UNIT
0
ns
5
ns
5
ns
5
ns
10
ns
28
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