THS10064 Datasheet, PDF (11/41 Pages) Texas Instruments – 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 – DECEMBER 1999
continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO. The first conversion value is written into the FIFO with a latency of 8 + TL (trigger level)
clock cycles after the FIFO reset.
Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case
of a trigger level set to 1 or 4.
Sample N
Channel 1
Sample N+1 Sample N+2 Sample N+3 Sample N+4 Sample N+5 Sample N+6 Sample N+7 Sample N+8
Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1
AIN
tw(CONV_CLKH)
CONV_CLK
Data Into
FIFO
td(A)
td(pipe)
tw(CONV_CLKL)
50%
50%
tc
Data N–5
Channel 1
Data N–4 Data N–3
Channel 1 Channel 1
DATA_AV,
Trigger Level = 1
DATA_AV,
Trigger Level = 4
td(O)
Data N–2 Data N–1
Channel 1 Channel 1
Data N
Channel 1
Data N+1 Data N+2
Channel 1 Channel 1
td(DATA_AV)
Data N+3
Channel 1
td(DATA_AV)
Figure 2. Timing of Continuous Conversion Mode (1-channel operation)
Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level set to 2 or 4.
Sample N
Channel 1,2
AIN
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
tw(CONV_CLKH)
CONV_CLK
td(A)
td(Pipe)
tw(CONV_CLKL)
50%
50%
tc
Data Into
FIFO
Data N–3
Channel 2
Data N–2 Data N–2
Channel 1 Channel 2
DATA_AV,
Trigger Level = 2
td(O)
Data N–1 Data N–1
Channel 1 Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
td(DATA_AV)
td(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
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