SLUA110 Datasheet, PDF (9/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
The actual deadtime is a summation of both the discharge
time of Ct and the width of the sync pulse. While being
applied, the sync pulse disables the PWM outputs and
must be added to the discharge time. The sync pulse width
can be used to compensate for the “lost” deadtime, or as
a deadtime extension.
T dead’ = T dchg’ + T sync pulse width
U-111
Top Trace:
Master :CT
Center Trace:
Clock Output
Bottom Trace:
V Sync Output
F OSC = 1 MHz
Figure 21. Circuit Timing Waveforms
Figure 19. Sync Circuit Schematic
Operating Principles
A positive going signal is input to the base of transistor Q1
which operates as an emitter follower. The leading edge of
the sync signal is coupled into the base of Q2 through
capacitor Cl, developing a voltage across R4 in phase with
the sync input. This signal is driven through C2 to the slave
timing capacitor and 24 ohm resistor network, forcing
synchronization of the slave to the master This high speed
pulse amplifier circuit adds a minimum of delay (= 50 ns)
between the master to slave timing relationship.
Top Trace:
Master Clock Output
Bottom Trace:
Slave Clock Output
Both: 1 V/CM, 20 ns/CM
Figure 22. Sync Circuit Delay; Input to Output
Vertical: 1 Volt/CM
Horizontal:
F OSC = 1 MHz
Figure 20. Sync Circuit Waveforms
This photo displays the waveforms of the sync circuit in
operation at a clock frequency of 1 megahertz. The top
trace is the circuit input, a 2.5 volt peak-to-peak clock out-
put signal from the UC3825 PWM. Any of several other
PWMs can be used as the source with similar results at
lower frequencies. The center trace depicts the base to
ground voltage waveform at transistor Q2, biased at 3 volts.
The lower trace displays the output voltage across R4 while
driving three slave modules, or about 8 ohms from the 5
volt reference.
Vertical: 1 V/CM All
Horizontal:
Fo = 1 MHz
Figure 23. Oscillator Waveforms:
Master and Slaves
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