SLUA110 Datasheet, PDF (4/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
U-111
Figure 8. Voltage & Current Waveforms at Gate
In a practical application, the transistors and other circuit
parameters, fortunately, are less than ideal. The results
above are unlikely to happen in most designs, however
they will occur at a reduced magnitude if not prevented.
Limiting the peak current through the IC is accomplished
by placing a resistor between the totem-pole output and
the gate of the MOSFET. The value is determined by divid-
ing the totem-pole collector voltage (Vc) by the peak
current rating of the IC’s totem-pole. Without this resistor,
the peak current is limited only by the dV/dT rate of the
totem-pole and the FET gate capacitance.
For this example, a collector supply voltage of 10 volts is
used, with an estimated totem-pole saturation voltage of
approximately 2 volts. Limiting the peak gate current to 1.5
amps max requires a resistor of six ohms, and the nearest
standard value of 6.2 ohms was used. Locating the resistor
in series with the collector to the auxiliary voltage source
will only limit the turn-on current. Therefore it must be
placed between the PWM and gate to limit both turn-on
and turn-off currents.
Actual circuit parasitics also play a key role in the drive
behavior. The inductance of the FET source lead (15 nano-
henries typical) is generally small in comparison to the lay-
out inductance. To model this network, an approximation of
30 nanohenries per inch of PC trace can be used. In addi-
tion, the inductance between the pins of the IC and the die
can be rounded off to 10 nanohenries per pin. It now
becomes apparent that circuit inductances can quickly
add up to 100 nanohenries, even with the best of PC lay-
outs. For this example, an estimate of 60 nh was used to
simulate the demonstration PC board. The equivalent cir-
cuit is shown in figure 10. A 10 volt pulse is applied to the
network using 6.2 ohms as the current limiting resistance.
Displayed is the resulting voltage and current waveform at
the totem-pole output.
Figure 9. Circuit Parameters
Figure 10. Circuit Response
The shaded areas of each graph are of particular interest.
During this time, the lower totem-pole transistor is satu-
rated. The voltage at its collector is negative with respect to
it’s emitter (ground). In addition, a positive output current is
being supplied to the RLC network thru this saturated NPN
transistor’s collector. The IC specifications indicate that
neither of these two conditions are tolerable individually,
nevermind simultaneously. One approach is to increase
the limiting resistance to change the response from under-
damped to slightly overdamped. This will occur when:
R (gate) 1 2 • JUC
Unfortunately, this also reduces the peak drive current,
thus increasing the switching times of the FETS - highly
undesirable. The alternate solution is to limit the peak
current, and alter the circuit to accept the underdamped
network.
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