SLUA110 Datasheet, PDF (3/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
Equating R1 to 1K ohm simplifies the above calculation
and selection of capacitor C2 for filtering the leading edge
glitch. Using the closest standard value to the calculated
value of R2 will minimally effect the exact amount of down-
slope introduced. It is important that R2 be high enough in
resistance not to load down the I.C. oscillator, thus causing
a frequency shift due to the slope compensation ramp
to R2.
Figure 6. Emitter Follower Circuit
Design Example — Slope Compensation Calculations
Circuit Description and Parameter Listing:
Topology: Half-Bridge Converter
Input Voltage: 85-132 VAC “Doubler Configuration”
Output: 5 VDC/45 ADC
Frequency: 200 KHz, T Period = 5.0 µS
T Deadtime: 500 ns, T on Max = 4.5 µS
Turns Ratio: 15/1, (Np/Ns)
V Primary: 90 VDC Min, 186 Max
V Sec Min: 6 VDC
R Sense: 0.25 Ohm
I Sec Ac: 3.0 Amps (<l0% I DC)
L Output: 5.16 µh
1. Calculate the Inductor Downslope on the
Secondary Side
S (L) = di/dt = Vs~c/Ls~c = 6 v/5.16 µh = 1.16 A/µs
2. Calculate the Transformed Inductor Slope to the
Primary Side
S (L)’ = S (L) • Ns/Np = 1.16 • 1/15 = 0.0775 A/µS
3. Calculate the Transformed Slope Voltage at
Sense Resistor
V S(L)’ = S (L)’ • Rsense = 7.72 • 1O^-2 • 0.250 =
1.94•10^-2 V/µS
U-111
4. Calculate the Oscillator Slope at the Timing Capacitor
S(osc) = d V osc/T on max = 1.8/4.5 = 0.400 V/µS
5. Let Amount of Slope Compensation (M) = 0.75 and
R1 = 1K
R2 = R1 • v %sc)
V S(L)’ • M
= 27.4 K ohms
; R2 = ^{1 K • 0.400}
0.0192 • 0.75
II. GATE DRIVE CIRCUITRY
The high current totem-pole outputs of most PWM ICs have
greatly enhanced and simplified MOSFET gate drive
circuits. Fast switching times of the high power FETs can
be attained with nearly a “direct” drive from the PWM.
Frequently overlooked, only two external components — a
resistor and Schottky diode are required to insure proper
operation of the PWM while delivering the high current
drive pulses.
MOSFET Input Impedance
Typical gate-to-source input characteristics of most FETs
reveal approximately 1500 picofarads of capacitance in
series with 15 nanohenries of source inductance. For this
example, the series gate current limiting resistor will not be
used to exemplify its necessity. Also, the totem pole tran-
sistors are replaced with ideal (lossless) switches. A dV/dT
rate of 0.5 volts per nanosecond is typical for most high
speed PWMs and will be incorporated.
Assuming no external circuit parasitics of R, L or C, the
PWM is therefore driving an L-C resonant tank with no
attenuation. The driving function is a 15 volt pulse derived
from the auxiliary supply voltage. The resulting current
waveform is shown in figure 8, having a peak current of
approximately seven amps at a frequency of thirty-three
megahertz.
3-108