SLUA110 Datasheet, PDF (1/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

9ul
B UNITRODE
APPLICATION NOTE
U-111
PRACTICAL CONSIDERATIONS IN
CURRENT MODE POWER SUPPLIES
Introduction
This detailed section contains an in-depth explanation of
the numerous PWM functions, and how to maximize their
usefulness. It covers a multitude of practical circuit design
considerations, such as slope compensation, gate drive
circuitry, external control functions, synchronization, and
paralleling current mode controlled modules. Circuit dia-
grams and simplified equations for the above items of inter-
est are included. Familiarity with these topics will simplify
the design and debugging process, and will save a great
deal of time for the power supply design engineer.
Constant Output Current
To maintain a constant AVERAGE current, independent of
duty cycle, a compensating ramp is required. Lowering the
error voltage precisely as a function of TON will terminate
the pulse width sooner. This narrows the duty cycle cre-
ating a CONSTANT output current independent of TON, or
VIN. This ramp simply compensates for the peak to aver-
age current differences as a function of duty cycle. Output
currents I1 and I2 are now identical for duty cycles D1 and
D2.
I. SLOPE COMPENSATION
Current mode control regulates the PEAK inductor current
via the ‘inner’ or current control loop. In a continuous mode
(buck) converter, however, the output current is the AVER-
AGE inductor current, composed of both an AC and DC
component.
While in regulation, the power supply output voltage and
inductance are constant. Therefore, VOUT / Ls~c and
dl/dT, the secondary ripple current, is also constant. In a
constant volt-second system, dT varies as a function of
VIN, the basis of pulse width modulation. The AC ripple
current component, dl, varies also as a function of dT in
accordance with the constant Vour Ls~c.
Average Current
At high values of VIN, the AC current in both the primary
and the secondary is at its maximum. This is represented
graphically by duty cycle D1, the corresponding average
current II, and the ripple current d(l1). As VIN decreases to
its minimum at duty cycle, the ripple current also is at its
minimum amplitude. This occurs at duty cycle D2 of aver-
age current I2 and ripple current d(I2). Regulating the
peak primary current (current mode control) will produce
different AVERAGE output currents I1, and I2 for duty
cycles D1 and D2. The average current INCREASES with
duty cycle when the peak current is compared to a fixed
error voltage.
Figure 2. Constant Average Current
Determining the Ramp Slope
Mathematically, the slope of this compensating ramp must
be equal to one-half (50%) the downslope of the output
inductor as seen from the control side of the circuit. This is
proven in detail in “Modelling, Analysis and Compensating
of the Current Mode Controller,” (Unitrode publication U-97
and its references). Empirically, slightly higher values of
slope compensation (75%) can be used where the AC
component is small in comparison to the DC pedestal, typi-
cal of a continuous converter
Circuit Implementation
In a current mode control PWM IC, the error voltage is gen-
erated at the output of the error amplifier and compared to
the primary current at the PWM comparator At this node,
subtracting the compensating ramp from the error voltage,
or adding it to the primary current sense input will have the
same effect: to decrease the pulse width as a function of
duty cycle (time). It is more convenient to add the slope
compensating ramp to the current input. A portion of the
oscillator waveform available at the timing capacitor (CT)
will be resistively summed with the primary current. This is
entered to the PWM comparator at the current sense input.
Figure 1. Average Current Error
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