SLUA110 Datasheet, PDF (8/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
The Timing Ramp
As mentioned, the timing ramp amplitude needs to be
approximately ten percent lower in frequency than normal.
Therefore, the MINIMUM sync pulse amplitude must fill the
remaining ten percent of the peak-to-peak ramp amplitude
to reach the upper threshold. Synchronization can be
insured over a wide range of frequency inputs and compo-
nent tolerances by supplying a slightly higher amplitude
sync pulse.
Lowering the peak-to-peak charging amplitude also lowers
the peak-to-peak discharge amplitude. This shortens the
time required to discharge Ct since it begins at a lower
potential. Consequently, this reduces the deadtime
accordingly. However, the sync pulse width adds to the IC
generated deadtime and increases the effective off, or
deadtime due to discharge. This sync pulse width need
only be wide enough to be sensed by the IC comparator,
which is fairly fast. Additional sync pulse width increases
deadtime which can be used to compensate for the 10%
lower ramp, hence deadtime.
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These equations can be reduced if an approximation is
made that the deadtime is very small in comparison to the
total period. In this case, the entire effect of changing the
ramp voltage is upon the charging time of the oscillator
Synchronizing to a higher frequency simply reduces the
charging time of Ct, (Tchg). The new charging time (Tchg’)
is the original charge time multiplied by the change in fre-
quency between F original and F sync. This relative
change will be used in several equations; it is labelled P, for
percentage of change.
For small values of charging current, or large values of Rt,
the voltage drop across the 24 ohm resistor is negligible. A
current of 2 milliamps will result in a 2.5% timing error with
a 2 volt peak to peak oscillator ramp at Ct. It is also prefer-
rable to free-run the IC oscillator at about a 15% lower fre-
quency than the synchronization frequency, where “P” =
0.85.
CHARGING RAMP
DISCHARGING RAMP
Figure 18. Oscillator Ramp Relationships
Oscillator Ramp Equations
The timing components required in the oscillator section
are generally determined graphically from the manufac-
turers’ data sheets for frequency and deadtime versus Rt
and Ct. While fine for most applications, a careful examina-
tion of the equations is necessary to analyze the impacts of
the additional sync circuit components on the timing
relationships.
With an approximate 2 volt peak to peak oscillator ampli-
tude, the minimum sync pulse amplitude is 0.30 volts for
synchronization to occur with a 15% latitude in
frequencies.
Oscillator Discharge Ramp Equations
Proper deadtime control in the switching power stage is
required to safeguard against catastrophic failures. Add-
ing the sync circuit to the oscillator reduces the discharge
time of the timing capacitor Ct, hence reducing the dead-
time of the PWM. There are two contributing factors. First,
the peak amplitude at the timing capacitor is lowered by AV
osc(o) - AVosc’, and the capacitor begins its discharge
from a lower potential. Second, the 24 ohm resistor adds
an offset voltage, dependent on its current. Typical IC dis-
charge currents range from approximately 6 to 12 milli-
amps. This offset due to charging current (1-2 ma) is low in
comparison to that of the discharge current (6 to 12 ma).
While negligible during the charge cycle, its tenfold effects
must be taken into account during the discharge, or
deadtime.
The discharge time (T dchg) can be calculated knowing
the discharge current of the particular IC. More convenient
is to use the manufacturers’ published deadtime listing for
a known value of Ct, and to calculate the effects of the sync
circuit. The discharge current has been averaged to 8 milli-
amps for brevity.
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