SLUA110 Datasheet, PDF (15/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
VII. HIGH EFFICIENCY START-UP CIRCUITS
FOR BOOTSTRAPPED POWER SUPPLIES
Many pulse width modulator I.C.s have been optimized for
offline use by incorporating an under-voltage lockout cir-
cuit. Demanding only a milliamp or two until start-up, the
auxiliary supply voltage (V aux) can be generated by a sim-
ple resistor/capacitor network from the high voltage dc rail
(+V dc). Once start-up is reached, the auxiliary power is
supplied by means of a “boostrap” winding on the main
transformer.
While the start-up requirements are quite low, losses in the
resistor to the high voltage DC can be significant in steady
state operation. This is especially true for low power (< 35
watt) applications and circuits with high voltage rails (400
volts DC, for example). Once the main converter is running,
switching the start-up resistor out of circuit would increase
efficiency substantially. Circuits have been developed to
use either bipolar or MOSFET transistors as the switch to
lower the start-up circuit power consumption, depending
on the application. Selection can be based on optimizing
circuit efficiency (MOSFET) or lowest component cost
(bipolar). The overall improvement in power supply effi-
ciency suggests this circuitry is a practical enhancement.
The high efficiency start-up circuit shown in figure 1 utilizes
two NPN bipolar transistors to switch the start-up resistor in
and out of circuit. It can be used in a variety of applications
with minor modifications, and requires a minimum of com-
ponents. Figure 2 displays a similar circuit utilizing N
channel MOSFET devices to perform the switching.
Figure 38. NPN Switches
U-111
Theory of Operation
Prior to applying the high voltage DC, capacitor Cl is dis-
charged; switches Q1, Q2 and the main converter are off.
As the input supply voltage (Vdc) rises, resistors R1 and R2
form a low current voltage divider. The voltage developed
across R2 rises accordingly with +V dc until switch Q1
turns on, thus charging C1 thru R start-up from +V dc. This
continues as the UV lockout threshold of the I.C. is reached
and the main converter begins operation. Energy is deli-
vered to Cl from the bootstrap winding in addition to that
supplied through R start-up.
After several cycles, the auxiliary voltage rises with the main
converters increasing pulse width, typical of a soft-start rou-
tine. Current flows through zener diode D1 and develops a
voltage across the Q2’s biasing resistor, R3. Transistor Q2
turns on when the auxiliary voltage reaches V zener plus
Q2’s turn on threshold. As this occurs, transistor Q1 is
turned off, thus eliminating the start-up resistor from the cir-
cuit power losses. In most applications, the auxiliary vol-
tage is optimized between 12 and 15 volts for driving the
main power MOSFETs, while keeping power dissipation in
the PWM IC low.
If the main converter is shut down for some reason, V aux
will decay until Q2 turns off. Transistor Q1 then turns back
on, and Cl is charged through R start-up from the high vol-
tage DC, as during start-up.
NOTE: SEE DESIGN NOTE DN-26 FOR ADDITIONAL
CIRCUITS.
VIII. CURRENT MODE
HALF BRIDGE APPLICATIONS
As previously described (1), current mode control can
cause a “runaway” condition when used with a “soft” cen-
tered primary power source. The best example of this is the
half bridge converter using two storage capacitors in series
from the rectified line voltage. For 110 VAC operation, the
input is configured as a voltage doubler, and one of the AC
inputs is tied directly to the storage capacitor’s centerpoint.
This is considered a “stiff” source, since the centerpoint will
remain at one-half of the developed voltage between the
upper and lower rail. However, during 220 VAC inputs, a
bridge configuration is used for the input rectifiers, and the
capacitors are placed in series with each other, across the
bridge. Their centerpoint potential will vary when different
amounts of charge are removed from the capacitors. This
is generally caused by uneven storage times in the switch-
ing transistors Q1 and Q2.
STIFF CENTERPOINT
Figure 39.
3-120
Figure 40.