SLUA110 Datasheet, PDF (6/19 Pages) Texas Instruments – PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES

APPLICATION NOTE
III. SYNCHRONIZATION
Power supplies have historically been thought of as “black
boxes,” an off-the-shelf commodity by most end users.
Their primary function is to generate a precise voltage,
independent of load current or input voltage variations, at
the lowest possible cost. In addition, end users allocate a
minimal amount of system real estate in which it must fit.
The major task facing design engineers is to overcome
these constraints while exceeding the customers’ expec-
tations, attaining high power densities and avoiding
thermal management problems. It is imperative, too, that
the power supply harmonize and integrate with the system
rather than cause catastrophic noise problems and last
minute headaches. Products that had performed to satis-
faction on the lab workbench powered by well filtered
linear supplies may not fare as well when driven by a noisy
switcher enclosed in a small cabinet.
Basic power supply design criteria such as the switching
frequency may be designated by the system clock or CPU
and thus may not be up to the power supply designer’s dis-
cretion. This immediately impacts the physical size of the
magnetic components, hence overall supply size, and may
result in less-than-optimum power density. However, for the
system to function properly, the power supply must be
synchronized to the system clock.
There are numerous other reasons for synchronizing the
power supply to the system. Most switching power noise
has a high peak-to-average ratio of short duration,
generally referred to as a spike. Common mode noise gen-
erated by these pulsating currents through stray capaci-
tance may be difficult (if not impossible) to completely elimi-
nate after the system design is complete. Ground loop
noise may also be amplified due to the interaction of
changing currents through parasitic inductances, resulting
in crosstalk through the system. EMI filtering to the main
input line is much simpler and more repeatable when
power is processed at a fixed frequency.
In addition, multiple power stages require synchronization
to reduce the differential noise generated between mod-
ules at turn-on. In unison, the converters begin their cycles
at the same time, each contributing to common mode
noise simultaneously, rather than randomly. This also sim-
plifies peak power considerations and will result in predict-
able power distribution and losses. Compensation made
for voltage drops along the bus bars, produced by both the
AC and DC power current components, can be accom-
plished. Balancing of the loads and power bus losses also
contributes to diminishing the differential noise and should
be administered for optimum results.
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Operation of the PWM Oscillator
In normal operation, the timing capacitor (Ct) is linearly
charged and discharged between two thresholds, the
upper and lower comparator thresholds. The charging
current is determined by means of a fixed voltage across
a user selected timing resistance (Rt). The resulting current
is then mirrored internally to the timing capacitor Ct at the
IC’s Ct output. The discharge current is internally set in
most PWM designs.
As Ct begins its charge cycle, the outputs of the PWM are
initiated and turn on. The timing capacitor charges, and
when its amplitude equals that of the error amplifier output,
the PWM output is terminated and the outputs turn off. Ct
continues to charge until it reaches the upper threshold of
the timing comparator Once intersected, the discharge
circuitry activates and discharges Ct until the timing
comparator lower threshold is reached. During this dis-
charge time, the PWM outputs are disabled, thus insuring
a “dead” time when each output is off.
The SYNC terminal provides a “digital” representation of
the oscillator charge/discharge status and can be utilized
as both an input or an output on most PWM’s. In instances
where no synchronization port is easily available, the timing
circuitry (Ct) can be driven from a digital (0V, 5V) logic input
rather than in the analog mode. The primary considera-
tions of on-time, off-time, duty cycle and frequency can be
encompassed in the digital pulse train. A LOW logic level
input determines the PWM ON time. Conversely, a HIGH
input governs the OFF time, or dead time. Critical con-
straints of frequency, duty cycle or dead time can be
accurately controlled by a digital signal to the PWM timing
cap (Ct) input. The command can be executed by anything
from a simple 555 timer, to an elaborate microprocessor
software controlled routine.
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