CDC921 Datasheet, PDF (9/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PCIx, 3V66x (Type 5)
PARAMETER
TEST CONDITIONS
VOH High-level output voltage
VDD = min to max,
VDD = 3.135 V,
VOL Low-level output voltage
VDD = min to max,
VDD = 3.135 V,
VDD = 3.135 V,
IOH High-level output current
VDD = 3.3 V,
VDD = 3.465 V,
VDD = 3.135 V,
IOL Low-level output current
VDD = 3.3 V,
VDD = 3.465 V,
CO Output capacitance
VDD = 3.3 V,
ZO Output impedance
High state
Low state
VO = 0.5 VDD,
VO = 0.5 VDD,
† _{All typical values are measured at their respective nominal VDD values.}
IOH = – 1 mA
IOH = –18 mA
IOL = 1 mA
IOL = 12 mA
VO = 1 V
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
VO = VDD or GND
VO/IOH
VO/IOL
MIN
VDD –
0.1 V
2.4
TYP†
0.15
–33 –53
–53
–16
30
67
70
27
4.5
12
31
12
24
MAX UNIT
V
0.1
V
0.4
mA
–33
mA
49
7.5 pF
55
Ω
55
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overshoot/undershoot
GND – 0.7 V
VDD + 0.7 V
V
Ring back
VIL – 0.1 V
VIH + 0.1 V
V
Stabilization time, PWR_DWN to PCIx f(CPU) = 133 MHz
0.05
3
ms
tdis3 Disable time, PWR_DWN to PCIx
f(CPU) = 133 MHz
50
ns
Stabilization time, PWR_DWN to CPUx f(CPU) = 133 MHz
0.03
3
ms
tdis4 Disable time, PWR_DWN to CPUx
f(CPU) = 133 MHz
50
ns
Stabilization time†
After SEL1, SEL0
After power up
3
ms
3
† _{Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for}
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
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