CDC921 Datasheet, PDF (5/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
functional block diagram
SEL133/100 ²⁵
SEL0 ²⁹
SEL1 ³⁰
Control
Logic
3-State
48-MHz Inactive
Test
SEL 133/100
XIN
XOUT
4
Xtal
5 ^Oscillator
SPREAD
31
Spread
Logic
48 MHz
PLL
CPU
PLL
/2
/2
2*REF
14.318 MHz
(1,2)
1*48MHz
48 MHz
(27)
3*CPU
100/133 MHz
(36,37,40)
1*CPU_DIV2
50/66 MHz
(43)
PWR_DWN ³²
/3
/4
/2
/3
/4
10*PCI
33 MHz
(7,8,10,11,12,
13,15,16,18,19)
1*APIC
16.67 MHz
(46)
3*AGP (3V66)
66 MHz
(21,22,23)
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