CDC921 Datasheet, PDF (2/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
description (continued)
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33 MHz.
Since the CDC921 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an
external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
Function Tables
INPUTS
SEL133/
100 ^SEL1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SEL0
L
H
L
H
L
H
L
H
CPU
Hi-Z
N/A
100 MHz
100 MHz
TCLK/2
N/A
133 MHz
133 MHz
CPU_DIV2
Hi-Z
N/A
50 MHz
50 MHz
TCLK/4
N/A
66 MHz
66 MHz
SELECT FUNCTIONS
OUTPUTS
3V66
PCI
48MHz
Hi-Z
N/A
66 MHz
66 MHz
TCLK/4
N/A
66 MHz
66 MHz
Hi-Z
N/A
33 MHz
33 MHz
TCLK/8
N/A
33 MHz
33 MHz
Hi-Z
N/A
Hi-Z
48 MHz
TCLK/2
N/A
Hi-Z
48 MHz
REF
APIC
FUNCTION
Hi-Z
Hi-Z
N/A
N/A
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
TCLK
TCLK/16
N/A
N/A
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
3-state
Reserved
48-MHz PLL off
48-MHz PLL on
Test
Reserved
48-MHz PLL off
48-MHz PLL on
INPUTS
PWR_DWN
L
H
CPU
L
On
ENABLE FUNCTIONS
OUTPUTS
CPU_DIV2 APIC 3V66 PCI
L
L
L
L
On
On
On
On
REF,
48MHz
L
On
INTERNAL
CRYSTAL VCOs
Off
Off
On
On
BUFFER NAME
CPU, CPU_DIV2, APIC
48MHz, REF
PCI, 3V66
OUTPUT BUFFER SPECIFICATIONS
VDD RANGE
(V)
IMPEDANCE
(Ω)
2.375 – 2.625
13.5 – 45
3.135 – 3.465
20 – 60
3.135 – 3.465
12 – 55
BUFFER TYPE
TYPE 1
TYPE 3
TYPE 5
2
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