CDC921 Datasheet, PDF (11/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
switching characteristics, V_DD = 2.375 V to 2.625 V, T_A = 0°C to 85°C (continued)
APIC
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1
tdis1
tc
tsk(p)
t(off)
Output enable time
Output disable time
APIC clock period†
Cycle to cycle jitter
Duty cycle
APIC pulse skew
APIC clock to CPU clock offset,
rising edge
SEL133/100
SEL133/100
APIC
APIC
APIC
CPUx
f(APIC) = 16.67 MHz
f(APIC) = 16.67 MHz
f(APIC) = 16.67 MHz
f(CPU) = 100 or 133 MHz
f(APIC) = 16.67 MHz
f(APIC) = 16.67 MHz
tw1
Pulse duration width, high
f(APIC) = 16.67 MHz
tw2
Pulse duration width, low
f(APIC) = 16.67 MHz
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 0.4 V to 2 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
60 60.24
45
–1.5
25.5
28
25.3 29.2
0.4 1.6
0.4 1.2
MAX
10
10
60.6
400
55
3
–4
2.1
1.7
UNIT
ns
ns
ns
ps
%
ns
ns
ns
ns
ns
ns
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C
3V66
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1
Output enable time
SEL133/100 3V66x
f(3V66) = 66 MHz
tdis1
tc
Output disable time
3V66 clock period†
SEL133/100 3V66x
f(3V66) = 66 MHz
f(3V66) = 66 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133 MHz
Duty cycle
f(3V66) = 66 MHz
tsk(o)
3V66 bus skew
3V66x
3V66x
f(3V66) = 66 MHz
tsk(p)
3V66 pulse skew
3V66n
3V66n
f(3V66) = 66 MHz
t(off)
3V66 clock to CPU clock offset 3V66x
CPUx
t(off)
3V66 clock to PCI clock offset, rising edge
tw1
Pulse duration width, high
f(3V66) = 66 MHz
tw2
Pulse duration width, low
f(3V66) = 66 MHz
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 0.4 V to 2 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP MAX UNIT
6
10 ns
8
10 ns
15 15.06 15.3 ns
400 ps
45
55 %
50 150 ps
2.6 ns
0 –0.75 –1.5 ns
1.2 2.1
3 ns
5.2
ns
5
ns
0.5 1.5
2 ns
0.5 1.5
2 ns
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