CDC921 Datasheet, PDF (10/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
switching characteristics, V_DD = 2.375 V to 2.625 V, T_A = 0°C to 85°C (continued)
CPUx
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1 Output enable time
SEL133/100 CPUx
f(CPU) = 100 or 133MHz
tdis1 Output disable time
SEL133/100 CPUx
f(CPU) = 100 or 133MHz
tc
CPU clock period†
f(CPU) = 100 MHz
f(CPU) = 133 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133MHz
Duty cycle
f(CPU) = 100 or 133MHz
tsk(o) CPU bus skew
CPUx
CPUx
f(CPU) = 100 or 133MHz
tsk(p) CPU pulse skew
CPUn
CPUn
f(CPU) = 100 or 133MHz
t(off) CPU clock to APIC clock offset, rising edge
t(off) CPU clock to 3V66 clock offset, rising edge
tw1 Pulse duration width, high
f(CPU) = 100 MHz
f(CPU) = 133 MHz
tw2 Pulse duration width, low
f(CPU) = 100 MHz
f(CPU) = 133 MHz
tr
Rise time
VO = 0.4 V to 2.0 V
tf
Fall time
VO = 0.4 V to 2.0 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
10 10.04
7.5 7.53
45
50
1.5 2.8
0 0.75
2.6 4.3
1.4 3.7
2.8 4.3
1.7
4
0.4 1.5
0.4 1.4
CPU_DIV2
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1 Output enable time
SEL133/100 CPU_DIV2 f(CPU) = 100 or 133MHz
tdis1 Output disable time
SEL133/100 CPU_DIV2 f(CPU) = 100 or 133MHz
tc
CPU_DIV2 clock period†
f(CPU) = 100 MHz
f(CPU) = 133 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133MHz
Duty cycle
f(CPU) = 100 or 133MHz
tsk(p) CPU_DIV2 pulse skew
f(CPU) = 100 or 133MHz
tw1 Pulse duration width, high
f(CPU) = 100 MHz
f(CPU) = 133 MHz
tw2 Pulse duration width, low
f(CPU) = 100 MHz
f(CPU) = 133 MHz
tr
Rise time
VO = 0.4 V to 2.0 V
tf
Fall time
VO = 0.4 V to 2.0 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
20 20.08
15 15.06
45
7.1
4.7
7.3 8.9
5 6.6
0.4 1.4
0.4 1.3
MAX
10
10
10.2
7.7
250
55
175
2.2
4
1.5
2.2
2
MAX
10
10
20.4
15.3
250
55
1.6
2
1.8
UNIT
ns
ns
ns
ns
ps
%
ps
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ps
%
ns
ns
ns
ns
ns
10
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