CDC921 Datasheet, PDF (1/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
D Generates Clocks for Pentium™ III Class
Microprocessors
D Supports a Single Pentium III
Microprocessor
D Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies
D Includes Spread Spectrum Clocking (SSC),
0.5% Downspread for Reduced EMI
Performance
D Power Management Control Terminals
D Low Output Skew and Jitter for Clock
Distribution
D Operates from Dual 2.5-V and 3.3-V
Supplies
D Generates the Following Clocks:
– 3 CPU (2.5 V, 100/133 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 1 CPU/2 (2.5 V, 50/66 MHz)
– 1 APIC (2.5 V, 16.67 MHz)
– 3 3V66 (3.3 V, 66 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 1 48MHz (3.3 V, 48 MHz)
D Packaged in 48-Pin SSOP Package
D Designed for Use with TI’s Direct Rambus™
Clock Generators (CDCR81, CDCR82,
CDCR83)
DL PACKAGE
(TOP VIEW)
REF0 1
REF1 2
V_DD3.3V 3
XIN 4
XOUT 5
GND 6
PCI0 7
PCI1 8
V_DD3.3V 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
GND 14
PCI6 15
PCI7 16
V_DD3.3V 17
PCI8 18
PCI9 ¹⁹
GND ²⁰
3V66(0) ²¹
3V66(1) ²²
3V66(2) ²³
V_DD3.3V ²⁴
48 GND
47 V_DD2.5V
46 APIC
45 GND
44 V_DD2.5V
43 CPU_DIV2
42 GND
41 V_DD2.5V
40 CPU2
39 GND
38 V_DD2.5V
37 CPU1
36 CPU0
35 GND
34 V_DD3.3V
33 GND
32 PWR_DWN
31 SPREAD
30 _SEL1
29 _SEL0
28 _VDD3.3V
27 _48MHz
26 _GND
25 _SEL133/100
description
The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF
system clock signals to support computer systems with a single Pentium III class microprocessor.
All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock
input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host
frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for
external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this
state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely with the outputs in a low-level output state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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