CDC921 Datasheet, PDF (12/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C (continued)
48MHz
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1
Output enable time
SEL133/100 48MHz
f(48MHz) = 48 MHz
tdis1
tc
Output disable time
48MHz clock period†
SEL133/100 48MHz
f(48MHz) = 48 MHz
f(48MHz) = 48 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133 MHz
Duty cycle
f(48MHz) = 48 MHz
tsk(p)
48MHz pulse skew
48MHz
48MHz
f(48MHz) = 48 MHz
tw1
Pulse duration width, high
f(48MHz) = 48 MHz
tw2
Pulse duration width, low
f(48MHz) = 48 MHz
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 0.4 V to 2 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
20.5 20.83
45
7.8
7.8
1 2.1
1 1.9
REF
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1
Output enable time
SEL133/100 REFx
f(REF) = 14.318 MHz
tdis1
tc
Output disable time
REF clock period†
SEL133/100 REFx
f(REF) = 14.318 MHz
f(REF) = 14.318 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133 MHz
Duty cycle
f(REF) = 14.318 MHz
tsk(o)
REF bus skew
REFx
REFx
f(REF) = 14.318 MHz
tsk(p)
REF pulse skew
REFn
REFn
f(REF) = 14.318 MHz
tw1
Pulse duration width, high
f(REF) = 14.318 MHz
tw2
Pulse duration width, low
f(REF) = 14.318 MHz
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 0.4 V to 2 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
69.84
45
150
26.2 32.7
26.2 31.2
1
2
1 1.9
MAX
10
10
21.1
500
55
3
2.8
2.8
MAX
10
10
700
55
250
2
2.8
2.8
UNIT
ns
ns
ns
ps
%
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ps
%
ps
ns
ns
ns
ns
ns
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