CDC921 Datasheet, PDF (13/17 Pages) Texas Instruments – 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS623 –MAY 27, 1999
switching characteristics, V_DD = 3.135 V to 3.465 V, T_A = 0°C to 85°C (continued)
PCI
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
ten1
Output enable time
SEL133/100 PCIx
f(PCI) = 33 MHz
tdis1
tc
Output disable time
PCIx clock period†
SEL133/100 PCIx
f(PCI) = 33 MHz
f(PCI) = 33 MHz
Cycle to cycle jitter
f(CPU) = 100 or 133 MHz
Duty cycle
f(PCI) = 33 MHz
tsk(o)
PCIx bus skew
PCIx
PCIx
f(PCI) = 33 MHz
tsk(p)
PCIx pulse skew
PCIn
PCIn
f(PCI) = 33 MHz
t(off)
PCIx clock to 3V66 clock offset
tw1
Pulse duration width, high
f(PCI) = 33 MHz
tw2
Pulse duration width, low
f(PCI) = 33 MHz
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 0.4 V to 2 V
† _{The average over any 1-µs period of time is greater than the minimum specified period.}
MIN TYP
6
8
30 30.12
45
70
–1.2
12
12
0.5 1.6
0.5 1.5
MAX
10
10
30.5
300
55
300
4
–3
2
2
UNIT
ns
ns
ns
ps
%
ps
ns
ns
ns
ns
ns
ns
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