TMS320DM6441_08 Datasheet, PDF (86/232 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
6.2 Recommended Operating Conditions
www.ti.com
MIN
NOM
MAX UNIT
CV_DD
Supply voltage, Core (CV_DD, V_{DDA_1P1V}, USB_V_DDA1P2LDO(1),
CV_DDDSP) ) ⁽²⁾
1.00
1.05
1.15
1.2
1.10
V
1.25
DV_DD
V_SS
DDR_VREF
DDR_ZP
DDR_ZN
DAC_VREF
Supply voltage, I/O, 3.3V (DV_DD33, USB_DV_DDA3P3)
Supply voltage, I/O, 1.8V (DV_DD18, DV_DDR2, DDR_V_DDDLL, PLLV_DD18,
V_{DDA_1P8V}, USB_V_DD1P8, MXV_DD, M24V_DD)
Supply ground (V_SS, V_{SSA_1P8V}, V_{SSA_1P1V}, DDR_V_SSDLL,
USB_V_SSREF, USB_V_SS1P8, USB_V_SSA3P3, USB_V_SSA1P2LDO,
MXV_SS ⁽³⁾, M24V_SS ⁽³⁾)
DDR2 reference voltage⁽⁴⁾
DDR2 impedance control, connected via 200 Ω resistor to V_SS
DDR2 impedance control, connected via 200 Ω resistor to DV_DDR2
DAC reference voltage input
3.15
3.3
1.71
1.8
0
0.49DV_DDR2
0.475
0
0.5DV_DDR2
V_SS
DV_DDR2
0.5
3.45 V
1.89 V
0V
0.51DV_DDR2
V
V
V
0.525 V
DAC_RBIAS
USB_VBUS
DAC biasing, connected via 4 kΩ resistor to V_{SSA_1P8V}
USB external charge pump input
4.75
V_{SSA_1P8V}
5
V
5.25 V
High-level input voltage, I/O, 3.3V
2
V_IH
V
High-level input voltage, non-DDR I/O, 1.8V
0.65DV_DD
Low-level input voltage, I/O, 3.3V
V_IL
Low-level input voltage, non-DDR I/O, 1.8V
0.8
V
0.35DV_DD
T_C
Operating case temperature
Default
0
85 C
1.05 V core
20
F_SYSCLK1
DSP Operating Frequency (SYSCLK1)
1.2 V core
20
405
MHz
513
(1) This pin is an internal LDO output and connected via 1 F capacitor to USB_V_SSA1P2LDO.
(2) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2, 1.26 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC
devices.
(3) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground.
(4) DDR_VREF is expected to equal 0.5DV_DDR2 of the transmitting device and to track variations in the DV_DDR2.
86
Device Operating Conditions
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