TMS320DM6441_08 Datasheet, PDF (77/232 Pages) Texas Instruments – Digital Media System-on-Chip

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VLYNQEN
0
0
0
0
1
1
1
TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
Table 4-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing
PINMUX0 REGISTER BIT FIELDS
VLSCREN
AECS5
-
0
-
0
-
1
-
1
0
-
0
-
1
-
AECS4
0
1
0
1
0
1
-
MULTIPLEXED PINS
EM_CS5/
GPIO[8]/
VLYNQ_CLOCK
EM_CS4/
GPIO[9]/
VLYNQ_SCRUN
GPIO[8]
GPIO[9]
GPIO[8]
EM_CS4
EM_CS5
GPIO[9]
EM_CS5
EM_CS4
VLYNQ_CLOCK
GPIO[9]
VLYNQ_CLOCK
EM_CS4
VLYNQ_CLOCK
VLYNQ_SCRUN
Table 4-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing
PINMUX0
REGISTER
BIT FIELDS
VLYNQEN VLYNQWD
0
-
1
00
EM_A[21]/
GPIO[10]/
VL_TXD0
EM_A[21]/
GPIO[10] ⁽¹⁾
VL_TXD0
1
01
VL_TXD0
1
10
VL_TXD0
EM_A[20]/
GPIO[11]/
VL_RXD0
EM_A[20]/
GPIO[11] ⁽¹⁾
VLRXD0
VLRXD0
VLRXD0
EM_A[19]/
GPIO[12]/
VL_TXD1
EM_A[19]/
GPIO[12] ⁽¹⁾
EM_A[19]/
GPIO[12] ⁽¹⁾
VL_TXD1
VL_TXD1
MULTIPLEXED PINS
EM_A[18]/
GPIO[13]/
VL_RXD1
EM_A[18]/
GPIO[13] ⁽¹⁾
EM_A[18]/
GPIO[13] ⁽¹⁾
VLRXD1
VLRXD1
EM_A[17]/
GPIO[14]/
VL_TXD2
EM_A[17]/
GPIO[14] ⁽¹⁾
EM_A[17]/
GPIO[14] ⁽¹⁾
EM_A[17]/
GPIO[14] ⁽¹⁾
VL_TXD2
1
11
VL_TXD0
VLRXD0
VL_TXD1
VLRXD1
VL_TXD2
(1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 4-9.
4.5.6.6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing
EM_A[16]/
GPIO[15]/
VL_RXD2
EM_A[16]/
GPIO[15] ⁽¹⁾
EM_A[16]/
GPIO[15] ⁽¹⁾
EM_A[16]/
GPIO[15] ⁽¹⁾
VLRXD2
VLRXD2
EM_A[15]/
GPIO[16]/
VL_TXD3
EM_A[15]/
GPIO[16] ⁽¹⁾
EM_A[15]/
GPIO[16] ⁽¹⁾
EM_A[15]/
GPIO[16] ⁽¹⁾
EM_A[15]/
GPIO[16] ⁽¹⁾
VL_TXD3
EM_A[14]/
GPIO[17]/
VL_RXD3
EM_A[14]/
GPIO[17] ⁽¹⁾
EM_A[14]/
GPIO[17] ⁽¹⁾
EM_A[14]/
GPIO[17] ⁽¹⁾
EM_A[14]/
GPIO[17] ⁽¹⁾
VLRXD3
The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 4-25.
Table 4-25. Timer0 Input, CLK_OUT1, and GPIO Pin
Multiplexing
PINMUX1 REGISTER BIT FIELDS
TIMIN
CLK1
0
0
0
1
1
-
MULTIPLEXED PINS
CLK_OUT1/
TIM_IN/
GPIO[49]
GPIO[49]
CLK_OUT1
TIM_IN
4.5.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing
When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as
seen in Table 4-26, Table 4-27, and Table 4-28. The SPI_EN1 pin can also function as the HDDIR buffer
control when ATAEN is selected and the HDIREN bit is set.
PINMUX1 REGISTER BIT FIELD
ASP
0
Table 4-26. ASP and GPIO Pin Multiplexing
CLKX/
GPIO[29]
GPIO[29]
CLKR/
GPIO[30]
GPIO[30]
MULTIPLEXED PINS
FSX/
GPIO[31]
FSR/
GPIO[32]
GPIO[31]
GPIO[32]
DX/
GPIO[33]
GPIO[33]
DR/
GPIO[34]
GPIO[34]
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