TMS320DM6441_08 Datasheet, PDF (70/232 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
www.ti.com
4.5.2 Multiplexed Pin Configurations
There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins
are configured by external pullup/pulldown resistors only at reset, and others are configured by software.
As described in detail in Section 4.4.1, Device Configuration at Device Reset, and Section 4.4.2,
Peripheral Selection at Device Reset, hardware configurable multiplexed pins are programmed by external
pullup/pulldown resistors at reset to set the initial functionality of pins for use by a single peripheral. After
reset, software configurable multiplexed pins are programmable through memory mapped registers (MMR)
to allow the switching of pin functionalities during run-time. See Section 4.5.3, Peripheral Selection After
Device Reset, for more details on the register settings.
A summary of the pin multiplexing is shown in Table 4-13. The EMAC peripheral shares pins with the 3.3V
GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address
range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals
with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and
PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional
pins to implement the RGB888 mode. These are multiplexed with GPIOs.
Table 4-13. DM6441 Multiplexed Peripheral Pins and Multiplexing Controls
MULTIPLEXED
PERIPHERALS
PRIMARY
(DEFAULT)
FUNCTION
SECONDARY ⁽¹⁾
FUNCTION
TERTIARY ⁽²⁾
FUNCTION
SECONDARY
REGISTER/PIN ⁽³⁾
CONTROL
EMIFA (NAND), HPI EMIFA:
HPI:
EM_A[1] (ALE), HHWIL, HCNTL0,
EM_A[2] (CLE)
HCS
EM_CS2, EM_CS3
PinMux0:HPIEN
Pins:BTSEL[1:0] = 10
EMIFA, HPI, ATA
(CF)
EMIFA:
EM_D[0:15],
EM_BA[0]
ATA (CF):
DD[0:15], DA0
HPI:
HD[0:15], HINT
PinMux0:ATAEN
EMIFA (NAND),
HPI, ATA (CF)
EMIFA (NAND):
R/W, EM_WAIT
(RDY/BSY),
EM_OE (RE),
EM_WE (WE)
ATA (CF):
INTRQ, IORDY,
DIOR(IORD) ,
DIOW (IOWR)
HPI:
PinMux0:ATAEN
HR/W, HRDY, HDS1,
HDS2
VPBE LCD, GPIO GPIO:GPIO[0]
VPBE: LCD_OE
PinMux0:LOEEN
VPFE CCD, GPIO GPIO:GPIO[1]
VPFE: C_WE
PinMux0:CWE
VPBE RGB888,
GPIO
GPIO:GPIO[2]
VPBE:
RGB888 G0
PinMux0:RGB888
VPBE
GPIO:GPIO[3]
LCD/RGB888, GPIO
VPBE:
RGB888 B0
VPBE:
LCD_FIELD
PinMux0:RGB888
VPFE CCD, VPBE GPIO:GPIO[4]
RGB888, GPIO
VPBE:
RGB888 R0
VPFE:
CCD_FIELD
PinMux0:RGB888
VPBE RGB888,
GPIO
GPIO:
GPIO[5:6, 38]
VPBE:
RGB888 G1, B1,
R1
PinMux0:RGB888
EMIFA, VLYNQ,
GPIO
GPIO:GPIO[8]
EMIFA:
EM_CS5
VLYNQ:
VLYNQ_CLOCK
PinMux0:AECS5
EMIFA, VLYNQ,
GPIO
GPIO:GPIO[9]
EMIFA:
EM_CS4
VLYNQ:
VLYNQ_SCRUN
PinMux0:AECS4
EMIFA, VLYNQ,
GPIO
GPIO:
GPIO[10:17]
EMIFA:
EM_A[21:14]
VLYNQ:
VLYNQ_TXD[0:3],
VLYNQ_RXD[0:3]
PinMux0:AEAW,
Pins:DAEAW[4:0]
EMIFA, GPIO
GPIO:
GPIO[18:28]
EMIFA:
EM_A[13:3]
PinMux0:AEAW,
Pins:DAEAW[4:0]
TERTIARY
REGISTER/PIN ⁽³⁾
CONTROL
PinMux0:HPIEN
PinMux0:HPIEN
PinMux0:LFLDEN
PinMux0:CFLDEN
PinMux0:VLYNQEN
PinMux0:VLSCREN
PinMux0:VLYNQEN,
PinMux0:VLYNQWD[1:0]
(1) When the secondary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO) and tertiary functions are
disabled.
(2) When the tertiary function is enabled, to avoid potential contention, ensure that the primary (if not GPIO), secondary, and other tertiary
functions are disabled.
(3) Pin states are sampled at power on reset and written into the register fields.
70
Device Configurations
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