TMS320DM6441_08 Datasheet, PDF (225/232 Pages) Texas Instruments – Digital Media System-on-Chip

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7.25.1 Host-Port Interface (HPI) Electrical Data/Timing
TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
Table 7-116. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾ (see Figure 7-81 through
Figure 7-82)
NO.
1 t_{su(SELV-HSTBL)}
2 t_{h(HSTBL-SELV)}
3 t_w(HSTBL)
4 t_w(HSTBH)
12 t_{su(HDV-HSTBH)}
13 t_h(HSTBH-HDV)
14 t_{h(HRDYL-HSTBH)}
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE high after HRDY low. HSTROBE should not
beinactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
1.05 V and 1.2
V
MIN MAX
5
2
15
2P
5
0
UNIT
ns
ns
ns
ns
ns
ns
2
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 405 MHz, use P = 1.48 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Table 7-117. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles⁽¹⁾ (see Figure 7-81 through Figure 7-82)
NO.
PARAMETER
1.05 V and 1.2 V
MIN
MAX
UNIT
6
t_{d(HSTBL-HRDYH)}
Delay time, HSTROBE low to HRDY high⁽²⁾
0
12
ns
7
t_{d(HSTBL-HDLZ)}
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
t_d(HDV-HRDYL)
Delay time, HD valid to HRDY low
0
ns
9
t_{oh(HSTBH-HDV)}
Output hold time, HD valid after HSTROBE high
1.5
ns
15 t_{d(HSTBH-HDHZ)}
Delay time, HSTROBE high to HD high impedance
4
ns
16 t_d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
15
ns
20 t_{d(HCSL-HRDYH)}
Delay time, HCS low to HRDY high
0
12
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling
edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the
EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer
is full.
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Peripheral and Electrical Specifications 225