TMS320DM6441_08 Datasheet, PDF (209/232 Pages) Texas Instruments – Digital Media System-on-Chip

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7.19.2 EMAC Electrical Data/Timing
TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
NO.
1 t_c(MRCLK)
2 t_w(MRCLKH)
3 t_w(MRCLKL)
Table 7-90. Timing Requirements for MRCLK (see Figure 7-65)
Cycle time, MRCLK
Pulse duration, MRCLK high
Pulse duration, MRCLK low
1.05 V and 1.2
V
MIN MAX
40
14
14
UNIT
ns
ns
ns
1
2
3
MRCLK
Figure 7-65. MRCLK Timing (EMAC - Receive)
NO.
1 t_c(MTCLK)
2 t_w(MTCLKH)
3 t_w(MTCLKL)
Table 7-91. Timing Requirements for MTCLK (see Figure 7-65)
Cycle time, MTCLK
Pulse duration, MTCLK high
Pulse duration, MTCLK low
1.05 V and 1.2
V
MIN MAX
40
14
14
UNIT
ns
ns
ns
1
2
3
MTCLK
Figure 7-66. MTCLK Timing (EMAC - Transmit)
Table 7-92. Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 7-67)
NO.
1 t_{su(MRXD-MRCLKH)}
Setup time, receive selected signals valid before MRCLK high
2 t_{h(MRCLKH-MRXD)}
Hold time, receive selected signals valid after MRCLK high
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
1.05 V and 1.2
V
MIN MAX
8
8
UNIT
ns
ns
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 7-67. EMAC Receive Interface Timing
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Peripheral and Electrical Specifications 209