TMS320DM6441_08 Datasheet, PDF (26/232 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
www.ti.com
3.7 Terminal Functions
The terminal functions tables (Table 3-5 through Table 3-30) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see Section 4, Device Configurations, of this data manual.
Table 3-5. BOOT Terminal Functions
SIGNAL
NAME
COUT0/
B3/
BTSEL0
COUT1/
B4/
BTSEL1
COUT2/
B5/
EM_WIDTH
COUT3/
B6/
DSP_BT
YOUT0/
G5/
AEAW0
YOUT1/
G6/
AEAW1
YOUT2/
G7/
AEAW2
YOUT3/
R3/
AEAW3
YOUT4/
R4/
AEAW4
NO.
TYPE⁽¹⁾ OTHER⁽²⁾⁽³⁾
DESCRIPTION
BOOT
These pins are multiplexed between ARM boot mode and the VPBE. At
reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to
A16
I/O/Z
IPD
DV_DD18
determine the ARM boot configuration. See below for the boot modes set
by these inputs. See Section 4.3, Bootmode for more details.
After reset, these are video encoder outputs COUT0 and COUT1, or
RGB666/888 Blue output data bits 3 and 4 B3/B4.
BTSEL1
BTSEL0
ARM Boot Mode
0
B16
I/O/Z
IPD
DV_DD18
0
1
0
ARM ROM boot (NAND) [default]
1
ARM EMIFA boot (NOR)
0
ARM ROM boot (HPI)
1
1
ARM ROM boot (UART0)
This pin is multiplexed between EMIFA and the VPBE. At reset, the input
state is sampled to set the EMIFA data bus width (EM_WIDTH). For an
A17
I/O/Z
IPD
DV_DD18
8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data
bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
data bit 5 B5.
This pin is multiplexed between DSP boot and the VPBE. At reset, the
input state is sampled to set the DSP boot source DSP_BT. The DSP is
B17
I/O/Z
IPD
DV_DD18
booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when
DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data
bit 6 output B6.
D15
I/O/Z
IPD
DV_DD18
D16
I/O/Z
IPD
DV_DD18
These pins are multiplexed between EMIFA and the VPBE. At reset, the
D17
I/O/Z
IPD
DV_DD18
input states of AEAW[4:0] are sampled to set the EMIFA address bus
width. See Section 4.4.2, Peripheral Selection at Device Reset, for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888
Red and Green data bit outputs G5, G6, G7, R3, and R4.
D18
I/O/Z
IPD
DV_DD18
E15
I/O/Z
IPD
DV_DD18
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal
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