CC2420 Datasheet, PDF (81/92 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

CC2420
38 Test Output Signals
The two digital output pins CCA and SFD,
can be set up to output test signals
defined by IOCFG1.CCAMUX and
IOCFG1.SFDMUX. This is summarized in
Table 12 and Table 13 below.
CCAMUX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Signal output on CCA pin
Description
CCA
Normal operation
ADC_Q[0]
ADC, Q-branch, LSB used for random number generation
DEMOD_RESYNC_LATE
High one 16 MHz clock cycle each time the demodulator
resynchronises late
LOCK_STATUS
Lock status, same as FSCTRL.LOCK_STATUS
MOD_CHIPCLK
Chip rate clock signal during transmission
MOD_SERIAL_CLK
Bit rate clock signal during transmission
FFCTRL_FS_PD
Frequency synthesizer power down, active high
FFCTRL_ADC_PD
ADC power down, active high
FFCTRL_VGA_PD
VGA power down, active high
FFCTRL_RXBPF_PD
Receiver bandpass filter power down, active high
FFCTRL_LNAMIX_PD
Receiver LNA / Mixer power down, active high
FFCTRL_PA_P_PD
Power amplifier power down, active high
AGC_UPDATE
High one 16 MHz clock cycle each time the AGC updates its gain
setting
VGA_PEAK_DET[1]
VGA Peak detector, gain stage 1
VGA_PEAK_DET[3]
VGA Peak detector, gain stage 3
AGC_LNAMIX_GAINMODE[1]
RF receiver front-end gain mode, bit 1
AGC_VGA_GAIN[1]
VGA gain setting, bit 1
VGA_RESET_N
VGA peak-detector reset sign, active low.
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
CLK_8M
8 MHz clock signal output
XOSC16M_STABLE
16 MHz crystal oscillator stabilised, same as the status bit in Table
5
FSDIG_FREF
Frequency synthesizer, 4 MHz reference signal
FSDIG_FPLL
Frequency synthesizer, 4 MHz divided signal
FSDIG_LOCK_WINDOW
Frequency synthesizer, lock window
WINDOW_SYNC
Frequency synthesizer, synchronized lock window
CLK_ADC
ADC clock signal 1
ZERO
Low
ONE
High
Table 12. CCA test signal select table
SWRS041B
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