CC2420 Datasheet, PDF (77/92 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

CC2420
FSTST0 (0x27) - Frequency Synthesizer Test Register 0
Bit
15:12
11
Field Name
-
VCO_ARRAY_SETTLE_LONG
Reset
0
0
10
VCO_ARRAY_OE
0
9:5
VCO_ARRAY_O[4:0]
16
4:0
VCO_ARRAY_RES[4:0] 16
R/W
W0
R/W
R/W
R/W
R
Description
Reserved, write as 0
When '1' this control bit doubles the time allowed for VCO
settling during VCO calibration.
VCO array manual override enable.
VCO array override value.
The VCO array result holds the register content of the most
recent calibration.
FSTST1 (0x28) - Frequency Synthesizer Test Register 1
Bit
15
Field Name
VCO_TX_NOCAL
Reset
0
14
VCO_ARRAY_CAL_LONG
1
13:10 VCO_CURRENT_REF[3:0]
4
9:4
VCO_CURRENT_K[5:0] 0
3
VC_DAC_EN
0
2:0
VC_DAC_VAL[2:0]
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0 : VCO calibration is always performed when going to RX or
when going to TX.
1 : VCO calibration is only performed when going to RX or when
using the STXCAL command strobe
When ‘1’ this control bit doubles the time allowed for VCO
frequency measurements during VCO calibration.
0 : PLL Calibration time is 37 us
1 : PLL Calibration time is 57 us
The value of the reference current calibrated against during VCO
calibration.
VCO current calibration constant. (Current B override value
when FSTST2.VCO_CURRENT_OE=1.)
Controls the source of the VCO VC node in normal operation
(TOPTST.VC_IN_TEST_EN=0):
0: Loop filter (closed loop PLL)
1: VC DAC (open loop PLL)
VC DAC output value
FSTST2 (0x29) - Frequency Synthesizer Test Register 2
Bit
15
14:13
Field Name
-
VCO_CURCAL_SPEED[1:0]
12
11:6
5:0
VCO_CURRENT_OE
VCO_CURRENT_O[5:0]
VCO_CURRENT_RES[5:0]
Reset R/W
0
W0
0
R/W
0
R/W
24
R/W
32
R
Description
Reserved, write as 0.
VCO current calibration speed:
0: Normal
1: Double speed
2: Half speed
3: Undefined.
VCO current manual override enable.
VCO current override value (current A).
The VCO current result holds the register content of the most
recent calibration.
SWRS041B
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