CC2420 Datasheet, PDF (30/92 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

CC2420
divided into three memory banks: TXFIFO
(bank 0), RXFIFO (bank 1) and security
(bank 2). The FIFO banks are 128 bytes
each, while the security bank is 112 bytes.
A6:0 is transmitted directly after the
RAM/Register bit as shown in Figure 9.
For RAM access, a second byte is also
required before the data transfer. This
byte contains B1:0 in bits 7 and 6,
followed by the R/W bit (0 for read+write, 1
for read). Bits 4 through 0 are don’t care
as shown in Figure 9.
For RAM write, data to be written must be
input on the SI pin directly after the
second address byte. RAM data read is
output on the SO pin simultaneously, but
may be ignored by the user if only writing
is of interest.
For RAM read, the selected byte(s) are
output on the SO pin directly after the
second address byte.
See Figure 10 for an illustration on how
multiple RAM bytes may be read or written
in one operation.
The RAM memory space is shown in
Table 6. The lower 256 bytes are used to
store FIFO data. Note that RAM access
should never be used for FIFO write
operations because the FIFO counter will
not be updated. Use RXFIFO and TXFIFO
access instead as described in section
FIFO access.
As with register data, data stored in RAM
will be retained during power down mode,
but not when the power-supply is turned
off (e.g. by disabling the voltage regulator
using the VREG_EN pin).
CSn:
Command strobe:
Multiple command strobes:
Read or write a whole register (16 bit):
Read 8 MSB of a register:
Multiple register read or write
Read or write n bytes from/to RF FIFO:
Read or write n bytes from/to RAM:
ADDR
ADDR
ADDR
ADDR
...
... ADDR
ADDR
ADDR DATA_8MSB DATA_8LSB
ADDR DATA_8MSB
ADDR DATA_8MSB DATA_8LSB
ADDR DATA_8MSB ...
ADDR DATA_8MSB DATA_8LSB
ADDR_FIFO DATA_byte0 DATA_byte1 DATA_byte2 DATA_byte3 ... DATA_{byte n-3} DATA_{byte n-2} DATA_{byte n-1}
ADDRL_RAM ADDRH_RAM DATA_ADDR DATA_ADDR+1 DATA_ADDR+2 ...
DATA_ADDR+n
Note:
FIFO and RAM access must be terminated with setting the CSn pin high.
Command strobes and register access may be followed by any other access,
since they are completed on the last negative edge on SCLK. They may however also be
terminated with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration
register.
Figure 10. Configuration registers write and read operations via SPI
SWRS041B
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