CC2420 Datasheet, PDF (28/92 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

CC2420
t_sp
t_ch
t_cl
t_sd
t_hd
t_ns
SCLK
CSn
Write to register / RXFIFO:
SI
0
0
A5 A4 A3 A2 A1 A0 X D_W15 D_W14 D_W13 D_W12 D_W11 D_W10 D_W9 D_W8 X D_W7 D_W6 D_W5 D_W4 D_W3 D_W2 D_W1 D_W0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
X
Write to TXFIFO:
SI
0
0
A5 A4 A3 A2 A1 A0 X D_W7 D_W6 D_W5 D_W4 D_W3 D_W2 D_W1 D_W0 X D_W7 D_W6 D_W5 D_W4 D_W3 D_W2 D_W1 D_W0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
S7
S6 S5 S4 S3 S2 S1 S0
S7
S6 S5 S4 S3 S2 S1 S0
S7
Read from register / RXFIFO:
SI
0
1 A5 A4 A3 A2 A1 A0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
D_R15 D_R14 D_R13 D_R12 D_R11 D_R10 D_R9 D_R8
D_R7
D_R6 D_R5 D_R4 D_R3 D_R2 D_R1 D_R0 D_R15
Read and write one byte to RAM: (multiple read / writes also possible)
SI
1 A6 A5 A4 A3 A2 A1 A0 X B1 B0 0
X
X
X
X
X X D_W7 D_W6 D_W5 D_W4 D_W3 D_W2 D_W1 D_W0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
X
D_R7
D_R6 D_R5 D_R4 D_R3 D_R2 D_R1 D_R0 D_R7
Read one byte from RAM: (multiple reads also possible)
SI
1 A6 A5 A4 A3 A2 A1 A0 X B1 B0 1
X
X
X
X
X
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
X
D_R7
D_R6 D_R5 D_R4 D_R3 D_R2 D_R1 D_R0 D_R7
Parameter
Symbol
Figure 9. SPI timing diagram
Min
Max Units
Conditions
SCLK, clock
frequency
F_SCLK
10
MHz
SCLK low
t_cl
25
pulse
duration
SCLK high
t_ch
25
pulse
duration
CSn setup
t_sp
25
time
ns
The minimum time SCLK must be low.
ns
The minimum time SCLK must be high.
ns
The minimum time CSn must be low before the first
positive edge of SCLK.
CSn hold time t_ns
25
SI setup time t_sd
25
ns
The minimum time CSn must be held low after the
last negative edge of SCLK.
ns
The minimum time data on SI must be ready
before the positive edge of SCLK.
SI hold time t_hd
25
ns
The minimum time data must be held at SI, after
the positive edge of SCLK.
Rise time
t_rise
100
ns
The maximum rise time for SCLK and CSn
Fall time
t_fall
100
ns
The maximum fall time for SCLK and CSn
Note: The set-up- and hold-times refer to 50% of VDD.
Table 4. SPI timing specification
13.3 Status byte
During transfer of the register access byte,
command strobes, the first RAM address
byte and data transfer to the TXFIFO, the
CC2420 status byte is returned on the SO
pin. The status byte contains 6 status bits
which are described in Table 5.
Issuing a SNOP (no operation) command
strobe may be used to read the status
byte. It may also be read during access to
chip functions such as register or FIFO
access.
SWRS041B
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