CC2420 Datasheet, PDF (31/92 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

CC2420
Address
0x16F –
0x16C
0x16B –
0x16A
0x169 –
0x168
0x167 –
0x160
0x15F –
0x150
0x14F –
0x140
0x13F –
0x130
0x12F –
0x120
0x11F –
0x110
0x10F –
0x100
0x0FF –
0x080
0x07F –
0x000
Byte Ordering
-
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB (Flags)
LSB
MSB
LSB
MSB
LSB
MSB (Flags)
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Name
-
Description
Not used
SHORTADR
16-bit Short address, used for address recognition.
PANID
16-bit PAN identifier, used for address recognition.
IEEEADR
CBCSTATE
64-bit IEEE address of current node, used for address
recognition.
Temporary storage for CBC-MAC calculations
TXNONCE / TXCTR
KEY1
Transmitter nonce for in-line authentication and
transmitter counter for in-line encryption.
Encryption key 1
SABUF
RXNONCE / RXCTR
KEY0
Stand-alone encryption buffer, for plaintext input and
ciphertext output
Receiver nonce for in-line authentication or
receiver counter for in-line decryption.
Encryption key 0
RXFIFO
128 bytes receive FIFO
TXFIFO
128 bytes transmit FIFO
Table 6. CC2420 RAM Memory Space
13.6 FIFO access
The TXFIFO and RXFIFO may be
accessed through the TXFIFO (0x3E) and
RXFIFO (0x3F) registers.
The TXFIFO is write only, but may be read
back using RAM access as described in
the previous section. Data is read and
written one byte at a time, as with RAM
access. The RXFIFO is both writeable and
readable. Writing to the RXFIFO should
however only be done for debugging or for
using the RXFIFO for security operations
(decryption / authentication).
The crystal oscillator must be running
when accessing the FIFOs.
setting the CSn pin high once it has been
started.
The FIFO and FIFOP pins also provide
additional information on the data in the
receive FIFO, as will be described in the
Microcontroller Interface and Pin
Description section on page 32. Note that
the FIFO and FIFOP pins only apply to
the RXFIFO. The TXFIFO has its
underflow flag in the status byte.
The TXFIFO may be flushed by issuing a
SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
receive FIFO.
13.7 Multiple SPI access
When writing to the TXFIFO, the status
byte (see Table 5) is output for each new
data byte on SO, as shown in Figure 9.
This could be used to detect TXFIFO
underflow (see section RF Data Buffering
section on page 39) while writing data to
the TXFIFO.
Multiple FIFO bytes may be accessed in
one operation, as with the RAM access.
FIFO access can only be terminated by
Register access, command strobes, FIFO
access and RAM access may be issued
continuously without setting CSn high.
E.g. the user may issue a command
strobe, a register write and writing 3 bytes
to the TXFIFO in one operation, as
illustrated in Figure 11. The only exception
is that FIFO and RAM access must be
terminated by setting CSn high.
SWRS041B
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