TLK2701 Datasheet, PDF (8/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS429B – AUGUST 2000 – REVISED MAY 2002
detailed description (continued)
receive data bus
The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data
is valid on the rising edge of the RX_CLK The RX_CLK is used as the recovered word clock. The data, enable,
and clock signals are aligned as shown in Figure 4. Detailed timing information can be found in the switching
characteristics table.
RX_CLK
RXD[0–15]
tsu
th
RXLSB, RXMSB
data reception latency
Figure 4. Receive Timing Waveform
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is
established. However, due to silicon process variations and implementation variables such as supply voltage
and temperature, the exact delay will vary slightly. The minimum receive latency (R_latency) is 76 bit times; the
maximum is 107 bit times. Figure 5 illustrates the timing relationship between the serial receive terminals, the
recovered word clock (RX_CLK), and the receive data bus.
20-Bit Encoded Word
DINTXP,
DINTXN
RXD[0–15]
(Rlatency)†
16-Bit Decoded Word
RX_CLK
Figure 5. Receiver Latency
serial-to-parallel
Serial data is received on the DINRXP and DINRXN terminals. The interpolator and clock recovery circuit will
lock to the data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock.
The recovered clock is used to retime the input data stream. The serial data is then clocked into the
serial-to-parallel shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate
8-bit/10-bit decoders where the data is then synchronized to the incoming data steam word boundary by
detection of the comma 8-bit/10-bit synchronization pattern.
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