TLK2701 Datasheet, PDF (4/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS429B – AUGUST 2000 – REVISED MAY 2002
Terminal Functions
TERMINAL
NAME
NO.
DINRXN
53
DINRXP
54
DOUTTXN
59
DOUTTXP
60
ENABLE
24
GND
GNDA
GTX_CLK
5, 13, 18,
28, 33, 43
52, 58, 61
8
LCKREFN
25
LOOPEN
21
PRBSEN
26
RREF
56
RXD0
51
RXD1
50
RXD2
49
RXD3
47
RXD4
46
RXD5
45
RXD6
44
RXD7
42
RXD8
40
RXD9
39
RXD10
37
RXD11
36
RXD12
35
RXD13
34
RXD14
32
RXD15
31
I/O
DESCRIPTION
I Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
O Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to copper
or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value.
DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when
LOOPEN is low. During power-on reset these terminals are high impedance.
I Device enable. When this terminal is held low, the device is placed in power-down mode. Only the signal
detect circuit on the serial receive pair is active. When asserted high while the device is in power-down
mode, the transceiver will go into power-on reset before beginning normal operation.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
I Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface signals TKMSB, TKLSB and TXD. The frequency range of GTX_CLK is 80 MHz to 135 MHz.
The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
I Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to GTX_CLK. This
places the device in a transmit only mode since the receiver is not tracking the data. When LCKREFN
is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RKLSB, RKMSB/LOS are in a
high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream.
I Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial
data is directly routed internally to the inputs of the receiver. This provides a self-test capability in
conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a high-impedance
state during the loop-back test. LOOPEN is held low during standard operational state with external serial
outputs and inputs active.
I PRBS test enable. When asserted high results of pseudo random bit stream (PRBS) tests can be
monitored on the RKLSB/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid PRBS is
being received.
I Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other side
of the resistor is connected to analog VDD. The resistor is used to provide an accurate current reference
to the transmitter and receiver I/O circuitry.
O Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the protocol
device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 11.
These terminals are in high-impedance state during power-on reset.
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