TLK2701 Datasheet, PDF (10/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS429B – AUGUST 2000 – REVISED MAY 2002
detailed description (continued)
power down mode
When the ENABLE pin is deasserted low, the TLK2701 will go into a power down mode. In the power down
mode, the serial transmit pins (DOUTTXP, DOUTTXN), the receive data bus pins (RXD[0:15]), and RKLSB will
go into a high-impedance state. In the power down condition, the signal detection circuit draws less than 15 mW.
When the TLK2701 is in the power-down mode, the clock signal on the GTX_CLK terminal must be provided.
loss of signal detection
The TLK2701 has a loss of signal detection circuit for conditions where the incoming signal no longer has a
sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be
an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not
an indication of signal coding health. The TLK2701 reports this condition by asserting, the RKMSB/LOS, RKLSB
and RXD[0:15] all to a high state. As long as the signal is above 200 mV in differential magnitude, the LOS circuit
will not signal an error condition.
PRBS verification
The TLK2701 also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can check
for errors and report the errors by forcing the RKLSB/PRBSPASS terminal low.
reference clock input
The reference clock (GTX_CLK) is an external input clock that synchronizes the transmitter interface. The
reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data
on both its rising and falling edge clock, providing a serial data rate that is 20 times the reference clock.
operating frequency range
The TLK2701 may operate at a serial data rate between 1.6 Gbps to 2.7 Gbps. The GTX_CLK must be within
±100 PPM of the desired parallel data rate clock.
testability
The TLK2701 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled
so that an I_DDQ test can be performed. The PRBS function allows for a BIST (built-in self-test).
loopback testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling
this terminal will cause serial-transmitted data to be routed internally to the receiver. The parallel data output
can be compared to the parallel input data for functional verification. (The external differential output is held in
a high-impedance state during the loopback testing.)
built-in self-test (BIST)
The TLK2701 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the RKLSB/
PRBS_PASS terminal.
power-on reset
Upon application of minimum valid power, the TLK2701 generates a power-on reset. During the power-on reset
the RXD, RKLSB, and RKMSB/LOS signal terminals go to a high-impedance state. The RX_CLK is held low.
The length of the power-on reset cycle is dependent upon the REFCLK frequency, but is less than 1 ms.
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