TLK2701 Datasheet, PDF (7/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS429B – AUGUST 2000 – REVISED MAY 2002
8-bit/10-bit encoder (continued)
The 8-bit/10-bit encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve its
transmission characteristics. Since the TLK2701 is a 16-bit wide interface, the data is split into two 8-bit wide
bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependant upon two additional
input signals, the TKMSB and TKLSB.
Table 1. Transmit Data Controls
TKLSB
0
0
1
1
TKMSB
0
1
0
1
DECODED 20 BIT OUTPUT
Valid data on TXD(0–7), Valid data TXD(8–15)
Valid data on TXD(0–7), K code on TXD(8–15)
K code on TXD(0–7),
Valid data on TXD(8–15)
K code on TXD(0–7),
K code on TXD(8–15)
PRBS generator
The TLK2701 has a built-in 2⁷-1 PRBS (pseudorandom bit stream) function. When the PRBSEN terminal is
forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter
input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then
fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent
to a BERT (bit error rate tester), the receiver of another TLK2701, or can be looped back to the receive input.
Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be
captured and checked for errors by a BERT.
parallel-to-serial
The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit
encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of
the internally generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (D0) is transmitted
first.
high-speed data output
The high-speed data output driver consists of a current-mode logic (CML) differential pair that can be optimized
for a particular transmission line impedance and length. The line can be directly-coupled or ac-coupled. Refer
to Figure 15 and Figure 16 for termination details.
receive interface
The receiver portion of the TLK2701 accepts 8-bit/10-bit encoded differential serial data. The interpolator and
clock recovery circuit will lock to the data stream and extract the bit rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7