TLK2701 Datasheet, PDF (5/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
TERMINAL
NAME
NO.
RX_CLK
41
RKLSB/
29
PRBS_PASS
RKMSB
TESTEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXD12
TXD13
TXD14
TXD15
TKMSB
TKLSB
VDD
VDDA
30
27
62
63
64
2
3
4
6
7
10
11
12
14
15
16
17
19
20
22
1, 9, 23,
38, 48
55, 57
SLLS429B – AUGUST 2000 – REVISED MAY 2002
Terminal Functions (Continued)
I/O
DESCRIPTION
O Recovered clock. Output clock that is synchronized to RXD, RKLSB, RKMSB/LOS. RX_CLK is
the recovered serial data rate clock divided by 20. RX_CLK is held low during power-on reset.
O K-Code indicator/PRBS test results. When RKLSB is active, an 8-bit/10-bit K code was received
and is indicated by data bits RXD0 –RXD7. When RKLSB is inactive an 8-bit/10-bit D code is
received and is presented on data bits RXD0 – RXD7.
When PRBSEN is asserted high then this pin is used to indicate status of the PRBS test results
(high = pass).
O K-code indicator. When RKMSB is active an 8-bit/10-bit K code was received and is indicated
by data bits RXD8 –RXD15. When RKMSB is inactive an 8-bit/10-bit D code was received and
is presented on data bits RXD8 – RXD15.
I Test mode enable. This terminal should be left unconnected or tied low.
I Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to
the transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked
into the transceiver on the rising edge of GTX_CLK as shown in Figure 10.
I K-code generator (MSB). When TKMSB is active an 8-bit/10-bit K code is transmitted as
controlled by data bits TXD8 –TXD15. When TKMSB is inactive an 8-bit/10-bit D code is
transmitted as controlled by data bits TXD8 – TXD15.
I K-code generator (LSB). When TKLSB is active an 8-bit/10-bit K code is transmitted as
controlled by data bits TXD0 –TXD7. When TKLSB is inactive an8-bit/10-bit D code is
transmitted as controlled by data bits TXD0 – TXD7.
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and
transmitter
detailed description
transmit interface
The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the GTX_CLK.
The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-speed
I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times, creating a
bit clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising
and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data is
transmitted LSB (D0) first.
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