TLK2701 Datasheet, PDF (6/21 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2701
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS429B – AUGUST 2000 – REVISED MAY 2002
detailed description (continued)
transmit data bus
The transmit bus interface accepts 16-bit single-ended TTL parallel data at the TXD[0:15] terminals. Data and
k-code control is valid on the rising edge of the GTX_CLK. The GTX_CLK is used as the word clock. The data,
k-code, and clock signals must be properly aligned as shown in Figure 2. Detailed timing information can be
found in the electrical characteristics table.
GTX_CLK
TXD[0–15]
tsu
th
TXLSB, TXMSB
Figure 2. Transmit Timing Waveform
transmission latency
The data transmission latency of the TLK2701 is defined as the delay from the initial 16-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay will vary
slightly. The minimum transmit latency (T_latency ) is 34 bit times; the maximum is 38 bit times. Figure 3 illustrates
the timing relationship between the transmit data bus, the GTX_CLK and serial transmit terminals.
Transmitted 20 bit Word
DOUTTXP,
DOUTTXN
TXD[0–15]
(Tlatency)†
16 bit Word to Transmit
GTX_CLK
Figure 3. Transmitter Latency
8-bit/10-bit encoder
All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving
PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc
balance by keeping the number of ones and zeros the same. This provides good transition density for clock
recovery and improves error checking. The TLK2701 uses the 8-bit/10-bit encoding algorithm that is used by
fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2701 internally encodes and
decodes the data such that the user reads and writes actual 16-bit data.
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