TLK1201IRCPRG4 Datasheet, PDF (8/22 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1201RCP, TLK1201IRCP
ETHERNET TRANSCEIVERS
SLLS506E − AUGUST 2001 − REVISED MAY 2007
receiver word alignment
This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word
alignment scheme. The following sections explain how this scheme works and how it realigns itself.
comma character on expected boundary
This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial
input data to the seven bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme
as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs (0011111),
referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.
As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly
aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1, SYNC,
and RD0−RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1).
comma character not on expected boundary
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following
the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in
Figure 5. The RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment.
With this design, the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when
the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing
characteristics of the data realignment.
Max Receive
Path Latency
31 Bit
Times
30 Bit
Times (Max)
INPUT DATA
K28.5 DXX.X DXX.X
K28.5 DXX.X DXX.X DXX.X K28.5
RBC0
RBC1
RD(0−9)
Worst Case
Misaligned K28.5
Corrupt Data
DXX.X DXX.X K28.5 DXX.X DXX.X
Misalignment Corrected
K28.5 DXX.X DXX.X DXX.X K28.5
SYNC
Figure 5. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the
SYNC pulse is present for the entire RBC0 period.
data reception latency
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times, and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is
34 bit times.
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