TLK1201IRCPRG4 Datasheet, PDF (3/22 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1201RCP, TLK1201IRCP
ETHERNET TRANSCEIVERS
block diagram
SLLS506E − AUGUST 2001 − REVISED MAY 2007
PRBSEN
LOOPEN
REFCLK
MODESEL
ENABLE
TESTEN
RBC1
RBC0
SYNC/PASS
PRBS
Generator
TD(0−9)
10 Bit
Registers
2:1
MUX
Control
Logic
PRBS
Verification
Parallel to
Serial
Clock
Phase Generator
Interpolator
and
Clock Extraction
Clock
RD(0−9)
Serial to Parallel
and
Comma Detect
2:1
MUX
Clock
2:1
MUX
SYNCEN
RBCMODE
JTMS
JTRSTN
JTDI
TCK
JTAG
Control
Register
JTDO
TXP
TXN
Data
RXP
RXN
LOS
TERMINAL
NAME
NO.
SIGNAL
MODESEL
15
LOS
26
RBCMODE
32
† _{P/D = Internal pulldown}
Terminal Functions
I/O
DESCRIPTION
I
P/D^†
O
I
P/D^†
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When
low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default
mode is the TBI.
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If magnitude of RXP−RXN > 150 mV, LOS = 1, valid input signal
If magnitude of RXP−RXN < 150 mV and > 50 mV, LOS is undefined
If magnitude of RXP−RXN < 50 mV, LOS = 0, loss of signal
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on
RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on
RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is
output on RBC0 and RBC1 is held low.
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