TLK1201IRCPRG4 Datasheet, PDF (5/22 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1201RCP, TLK1201IRCP
ETHERNET TRANSCEIVERS
SLLS506E − AUGUST 2001 − REVISED MAY 2007
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TEST (continued)
JTRSTN
56
LOOPEN
19
PRBSEN
16
TCK
49
TESTEN
17
POWER
VDD
5, 10, 20,
23, 29, 37,
42, 50, 63
VDDA
53, 57, 59,
60
VDDPLL
18
GROUND
GND
1, 14, 21,
25, 33, 46
GNDA
51, 58
GNDPLL
64
† _{P/D = Internal pulldown}
‡ _{P/U = Internal pullup}
I/O
I
P/U^‡
I
P/D^†
I
P/D^†
I
I
P/D^†
Supply
Supply
Supply
Ground
Ground
Ground
DESCRIPTION
Reset signal. IEEE1149.1 (JTAG)
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted
serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction
with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the
loop-back test. LOOPEN is held low during standard operational state with external serial outputs and
inputs active.
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification
circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for
errors, that are reported by the SYNC/PASS terminal indicating low.
Test clock. IEEE1149.1 (JTAG)
Manufacturing test terminal
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.
PLL ground. Provides a ground for the PLL circuitry.
detailed description
data transmission
This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.
When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0−TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0−TD4. In this mode, data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bit 0−4, and the falling edge of REFCLK clocks in bits
5−9. (Bit 0 is the first bit transmitted).
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