TMS320DM647_10 Datasheet, PDF (71/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
www.ti.com
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
6.6 Enhanced Direct Memory Access (EDMA3) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
• Transfer to/from on-chip memories
– DSP L1D memory
– DSP L2 memory
• Transfer to/from external storage
– DDR2 SDRAM
– Synchronous/Asynchronous EMIF (EMIFA)
• Transfer to/from peripherals/hosts
– VLYNQ
– HPI
– McASP
– UART
– Video Port 0/1/2/3/4
– Timer 0/1/2/3
– SPI
– I2C
6.6.1 EDMA3 Channel Synchronization Events
The EDMA supports up to 64 EDMA channels that service peripheral devices and external memory.
Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. The association of an event to a channel is fixed; each of the EDMA channels has one
specific event associated with it. These specific events are captured in the EDMA event registers (ER,
ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more
detailed information on the EDMA module and how EDMA events are enabled, captured, processed,
linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced DMA (EDMA)
Controller User's Guide (literature number SPRUEL2).
Table 6-13. EDMA Channel Synchronization Events
TPCC DEFAULT BINARY
CHANNEL EVENT#
0
0
000 0000
1
1
000 0001
2
2
000 0010
3
3
000 0011
4
4
000 0100
5
5
000 0101
6
6
000 0110
7
7
000 0111
8
8
000 1000
9
9
000 1001
10
10
000 1010
11
11
000 1011
12
12
000 1100
13
13
000 1101
14
14
000 1110
15
15
000 1111
DEFAULT EVENT
HPI/PCI : DSPINT
TIMER0 : TINT0L
TIMER0 : TINT0H
TIMER2 : TINT2L
TIMER2 : TINT2H
TIMER3 : TINT3L
TIMER3 : TINT3H
VICP: IMXINT
VICP: VLCDINT
VICP: DSQINT
McASP: AXEVTE
McASP: AXEVTO
McASP: AXEVT
McASP: AREVTE
McASP: AREVTO
McASP: AREVT
TPCC DEFAULT BINARY
CHANNEL EVENT #
32
32
010 0000
33
33
010 0001
34
34
010 0010
35
35
010 0011
36
36
010 0100
37
37
010 0101
38
38
010 0110
39
39
010 0111
40
40
010 1000
41
41
010 1001
42
42
010 1010
43
43
010 1011
44
44
010 1100
45
45
010 1101
46
46
010 1110
47
47
010 1111
DEFAULT EVENT
VP2EVTYA
VP2EVTCbA
VP2EVTCrA
VP2EVTYB
VP2EVTCbB
VP2EVTCrB
VP3EVTYA
VP3EVTCbA
VP3EVTCrA
VP3EVTYB
VP3EVTCbB
VP3EVTCrB
ICREVT
ICXEVT
SPI: SPIXEVT
SPI: SPIREVT
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Peripheral Information and Electrical Specifications
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