TMS320DM647_10 Datasheet, PDF (59/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
www.ti.com
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner.
6.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/dsppower.
6.3.1 Power-Supply Sequencing
The device includes 1.2-V core supply (CV_DD, CV_DDESS, CV_DD1, AV_DDA, DV_DDD, AV_DDT), and two I/O
supplies—3.3-V (DV_DD33) and 1.8-V (DV_DD18, AV_DLL1, AV_DLL2, AV_DDR). To ensure proper device operation,
a specific power-up sequence must be followed. Some TI power-supply devices include features that
facilitate power sequencing — for example, Auto-Track and Slow-Start/Enable features. For more
information on TI power supplies and their features, visit www.ti.com/dsppower.
Following is a summary of the power sequencing requirements:
• The power ramp order must be 3.3-V (DV_DD33) before 1.8-V (DV_DD18, AV_DLL1, AV_DLL2, AV_DDR), and
1.8-V (DV_DD18, AV_DLL1, AV_DLL2, AV_DDR) before 1.2-V core supply (CV_DD, CV_DDESS, CV_DD1, AV_DDA,
DV_DDD, AV_DDT) —meaning during power up, the voltage at the 1.8-V rail should never exceed the
voltage at the 3.3-V rail. Similarly, the voltage at the 1.2-V rail should never exceed the voltage at the
DV_DDR2 rail.
• From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within
200 ms. The term "stable" means reaching the recommended operating condition (see Section 5.2).
6.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the device, the PC board should include separate power planes for core, I/O, and ground; all
bypassed with high-quality low-ESL/ESR capacitors.
6.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors; therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large
bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for
each supply should be placed outside of the BGA footprint.
6.3.4 Power and Sleep Controller (PSC)
The power and sleep controller (PSC) controls power by turning off unused power domains or by gating
off clocks to individual peripherals/modules. The device uses the clock-gating feature of the PSC only for
power savings. The PSC consists of a global PSC (GPSC) and a set of local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. The LPSCs are shown in Table 6-2. The PSC register memory map is given in Table 6-3. For
more details on the PSC, see the TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide
(literature number SPRUEU6).
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Peripheral Information and Electrical Specifications
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