TMS320DM647_10 Datasheet, PDF (64/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
www.ti.com
The device architecture is divided into the power and clock domains shown in Table 6-5, which further
shows the clock domains and their ratios.
Table 6-5. Clock Domain Assignment
SUBSYSTEM
CLOCK DOMAIN
DOMAIN CLOCK SOURCE
FIXED RATIO vs SYSREFCLK
FREQUENCY
DSP Subsystem
CLKDIV1
PLLC1.REFSYSCLK
-
Peripherals (CLKDIV3 Domain)
CLKDIV3
PLLC1.SYSCLK1
1:3
Emulation/Trace
CLKDIV4 1
PLLC1.SYSCLK2
1:4
Peripherals (CLKDIV6 Domain)
Internal EMIFA Clock
CLKDIV6
CLKDIV4 0
PLLC1.SYSCLK3
PLLC1.SYSCLK4
1:6
1:4 ⁽¹⁾
VICP cop_clk/2
CLKDIV4 2
PLLC1.SYSCLK5
1:4
VICP cop_clk
CLKDIV2
PLLC1.SYSCLK6
1:2
(1) There is a /2 divider in the path of PLLC1.SYSCLK4 so the effective EMIFA clock is PLLC1.SYSCLK4/2. By default the internal EMIFA
Clock is 1:8.
6.3.6 Preserving Boundary-Scan Functionality on DDR2 Memory Pins
Similarly, when the DDR2 Memory Controller is not used, the DDR_VREF, RSV19, and RSV20 pins can
be connected directly to ground (V_SS) to save power. However, this will prevent boundary-scan from
functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2
Memory Controller pins, DDR_VREF, RSV19, and RSV20 should be connected as follows:
• DDR_VREF - connect to a voltage of DV_DD18/2. The DV_DD18/2 voltage can be generated directly from
the DV_DD18 supply using two 1-kΩ resistors to form a resistor divider circuit.
• RSV19 - connect this pin to the 1.8-V I/O supply (DV_DD18) via a 200-Ω resistor
• RSV20 - connect this pin to ground (V_SS) via a 200-Ω resistor.
64
Peripheral Information and Electrical Specifications
Copyright © 2010–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648