TMS320DM647_10 Datasheet, PDF (120/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
6.12.3 VIC Electrical Data/Timing
6.12.3.1 STCLK Timing
Table 6-55. Timing Requirements for STCLK⁽¹⁾ (see Figure 6-32)
NO.
1 t_c(STCLK)
Cycle time, STCLK
2 t_w(STCLKH)
Pulse duration, STCLK high
3 t_w(STCLKL)
Pulse duration, STCLK low
4 t_t(STCLK)
Transition time, STCLK
(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
1
2
3
STCLK
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-720
-800
-900
-1100
MIN MAX
33.3
16
16
3
UNIT
ns
ns
ns
ns
4
4
Figure 6-32. STCLK Timing
120 Peripheral Information and Electrical Specifications
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