TMS320DM647_10 Datasheet, PDF (130/181 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009
www.ti.com
Table 6-63. Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 6-39)
NO.
16
t_c(SCL)
17
t_d(SCLH-SDAL)
18
t_d(SDAL-SCLL)
19
t_w(SCLL)
20
t_w(SCLH)
21
t_d(SDAV-SCLH)
22
t_v(SCLL-SDAV)
23
t_w(SDAH)
24
t_r(SDA)
PARAMETER
Cycle time, SCL
Delay time, SCL high to SDA low (for a repeated START
condition)
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START
conditions
Rise time, SDA
720, 800, 900, 1100
STANDARD
MODE
FAST MODE
MIN MAX
MIN MAX
10
2.5
UNIT
µs
4.7
0.6
µs
4
0.6
µs
4.7
1.3
µs
4
0.6
µs
250
100
ns
0
0 0.9 µs
4.7
1.3
µs
1000
20 + 0.1C_b
(1)
300
ns
25
t_r(SCL)
Rise time, SCL
1000
20 + 0.1C_b
(1)
300
ns
26
t_f(SDA)
Fall time, SDA
300
20 + 0.1C_b
(1)
300
ns
27
t_f(SCL)
Fall time, SCL
300
20 + 0.1C_b
(1)
300
ns
28
t_d(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
4
29 C_p
Capacitance for each I2C pin
10
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
0.6
µs
10 pF
26
24
SDA
23
21
19
28
25
20
SCL
16
27
18
22
17
18
Stop Start
Repeated
Start
Stop
Figure 6-39. I2C Transmit Timings
130 Peripheral Information and Electrical Specifications
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