TMS320DM6441 Datasheet, PDF (7/229 Pages) Texas Instruments – Digital Media System-on-Chip

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2 Device Overview
TMS320DM6441
Digital Media System-on-Chip
SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007
2.1 Device Characteristics
Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the
device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the
C64x+ DSP, and the package type with pin count.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DDR2 Memory Controller
Asynchronous EMIF (EMIFA)
Flash Cards
EDMA
Peripherals
Timers
Not all peripherals pins
are available at the
same time (For more
detail, see the Device
Configuration section).
UART
SPI
I²C
Audio Serial Port [ASP]
10/100 Ethernet MAC with Management Data Input/Output
VLYNQ
HPI
General-Purpose Input/Output Port
PWM
ATA/CF
Configurable Video Ports
USB 2.0
Size (Bytes)
On-Chip Memory
Organization
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16])
JTAG BSDL_ID
JTAGID register
(address location: 0x01C4 0028)
CPU Frequency
MHz
Cycle Time
ns
DM6441
DDR2 (16/32-bit bus width)
Asynchronous (8/16-bit bus width) RAM, Flash
(NOR, NAND)
Compact Flash
MMC/SD with secure data input/output (SDIO)
SmartMedia/xD
Memory Stick/Memory Stick Pro
64 independent channels
8 QDMA channels
2 64-bit general purpose (each configurable as 2
separate 32-bit timers)
64-bit watch dog
3 (one with RTS and CTS flow control)
1 (supports 2 slave devices)
1 (master/slave)
1
1
1
1 (16-bit multiplexed address/data)
Up to 71
3 outputs
1 (ATA/ATAPI-5)
1 input (VPFE)
1 output (VPBE)
High speed client
160KB RAM, 8KB ROM
DSP
• 32KB L1 program (L1P)/cache (up to 32KB)
• 80KB L1 data (L1D)/cache (up to 32KB)
• 64KB unified mapped RAM/cache (L2)
ARM
• 16KB I-cache
• 8KB D-cache
• 16KB RAM
• 8KB ROM
0x1000
0x0B70 002F
DSP 405 MHz , ARM 202.5 MHz at 1.05 V
DSP 513 MHz, ARM 256 MHz at 1.2 V
DSP 2.47 ns, ARM 4.94 ns at 1.05 V
DSP 1.9 ns, ARM 3.9 ns at 1.2V
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Device Overview
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