TMS320DM6441 Datasheet, PDF (60/229 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007
www.ti.com
3.3.3 DSP Boot
For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be
the master of C64x+ and control booting (host-boot mode). If DSP_BT is high, the C64x+ will boot itself
coming out of device reset (self-boot mode). Table 3-7 shows a summary of the DSP boot modes.
Table 3-7. DSP Boot Modes
DSP_BT
0
DSP
Boot Mode
Host boot
ARM
Boot Mode
Internal boot
0
Host boot
External boot
1
Self boot
Any, except HPI
1
Host boot
HPI
3.3.3.1 Host-Boot Mode
DSPBOOTADDR
Register Value
Programmable
Programmable
0x4220 0000
Programmable
Brief Description
ARM sets an internal DSP memory location in DSPBOOTADDR
register where valid DSP code resides and loads code to this
internal DSP memory through DMA prior to releasing DSP reset.
ARM sets an external DSP memory location in DSPBOOTADDR
register (EMIFA or DDR2) where valid DSP code resides prior to
releasing DSP reset.
Default EMIFA base address
ARM sets a DSP memory location in the DSPBOOTADDR
register.
HPI loads code into the DM6441 memory map with the entry point
set to the memory location specified in the DSPBOOTADDR
register. Once the HPI completes loading the code, the ARM
should release the DSP from reset.
3.3.3.2 Self-Boot Mode
In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset
without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000)
contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache
enabled.
3.4 Configurations at Reset
The following sections give information on configuration settings for the device at reset.
3.4.1 Device Configuration at Device Reset
Table 3-8 shows a summary of device inputs required for booting the ARM and DSP, and configuring
EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET
input.
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Device Configurations
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