TMS320DM6441 Datasheet, PDF (26/229 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007
www.ti.com
SIGNAL
NAME
TRST
EMU1
EMU0
Table 2-8. RESET and JTAG Terminal Functions (continued)
NO.
TYPE⁽¹⁾ OTHER^{(2) (3)}
DESCRIPTION
D7
I
C6
I/O/Z
D6
I/O/Z
IPD
DV_DD18
IPU
DV_DD18
IPU
DV_DD18
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG compatibility statement portion of this data manual .
Emulation pin 1
Emulation pin 0
Table 2-9. EMIFA Terminal Functions
SIGNAL
TYPE ⁽¹⁾
NAME
NO.
COUT2/
B5/
EM_WIDTH
A17 I/O/Z
COUT3/
B6/
DSP_BT
YOUT0/
G5/
AEAW0
YOUT1/
G6/
AEAW1
YOUT2/
G7/
AEAW2
YOUT3/
R3/
AEAW3
YOUT4/
R4/
AEAW4
B17 I/O/Z
D15 I/O/Z
D16 I/O/Z
D17 I/O/Z
D18 I/O/Z
E15 I/O/Z
EM_CS2
C2 I/O/Z
EM_CS3
B1
EM_CS4/
GPIO9/
T2
VLYNQ_SCRUN
EM_CS5/
GPIO8/
T1
VLYNQ_CLOCK
EM_R/W/
INTRQ
G3
HR/W
I/O/Z
I/O/Z
I/O/Z
I/O/Z
OTHER ⁽²⁾
DESCRIPTION
DV_DD18
DV_DD18
EMIFA BOOT CONFIGURATION
This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is
sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA
data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5
B5.
This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is
sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when
DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output
B6.
DV_DD18
DV_DD18
DV_DD18
DV_DD18
These pins are multiplexed between EMIFA and the VPBE. At reset, the input states
of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2,
Peripheral Selection at Device Reset for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and
Green data bit outputs G5, G6, G7, R3, and R4.
DV_DD18
EMIFA FUNCTIONAL PINS: ASYNC / NOR
DV_DD18
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous
memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.
DV_DD18
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
memories (i.e., NOR flash) or NAND flash. In HPI mode, this pin must be pulled high
via an external 10-kΩ resistor.
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
DV_DD18
This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories
(i.e., NOR flash) or NAND flash.
DV_DD18
This pin is multiplexed between EMIFA and ATA/CF.
For EMIFA, it is read/write output EM_R/W.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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