TMS320DM6441 Datasheet, PDF (104/229 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007
www.ti.com
5.7 Interrupts
The DM6441 device has a large number of interrupts to service the needs of its many peripherals and
subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device
interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt
controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical
applications, the ARM handles most of the peripheral interrupts and grants control, to the C64x+, of
interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other
through interrupts.
5.7.1 ARM CPU Interrupts
The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The DM6441 ARM interrupt controller
prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in
Table 5-18, and interrupts the ARM CPU. Each interrupt is programmable for up to eight levels of priority.
There are six levels for IRQ and two levels for FIQ. Interrupts at the same priority level are serviced in
order by the ARM Interrupt Number, with the lowest number having the highest priority. Table 5-19 shows
the ARM interrupt controller registers and memory locations. For more details on ARM interrupt control,
see Section 2.8.3, Documentation Support, for the TMS320DM644x ARM Subsystem Reference Guide.
104 Peripheral and Electrical Specifications
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