TMS320DM6441 Datasheet, PDF (17/229 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6441
Digital Media System-on-Chip
SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007
Table 2-3. Memory Map Summary
START
ADDRESS
0x0000 0000
0x0000 2000
0x0000 4000
0x0000 6000
0x0000 8000
0x0000 A000
0x0000 C000
0x0000 E000
0x0001 0000
0x0010 0000
0x0020 0000
0x0080 0000
0x0081 0000
0x00E0 8000
0x00E1 0000
0x00F0 4000
0x00F1 0000
0x00F1 8000
0x0180 0000
0x01BC 0000
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01C0 0000
0x0200 0000
0x0A00 0000
0x0C00 0000
0x1000 0000
0x1000 8000
0x1000 A000
0x1000 C000
0x1000 E000
0x1001 0000
0x1110 0000
0x1120 0000
0x1180 0000
0x1181 0000
0x11E0 8000
0x11E1 0000
0x11F0 4000
0x11F1 0000
0x11F1 8000
0x2000 0000
0x2000 8000
0x4200 0000⁽¹⁾
0x5000 0000
0x8000 0000
0x9000 0000
END
ADDRESS
0x0000 1FFF
0x0000 3FFF
0x0000 5FFF
0x0000 7FFF
0x0000 9FFF
0x0000 BFFF
0x0000 DFFF
0x0000 FFFF
0x000F FFFF
0x001F FFFF
0x007F FFFF
0x0080 FFFF
0x00E0 7FFF
0x00E0 FFFF
0x00F0 3FFF
0x00F0 FFFF
0x00F1 7FFF
0x017F FFFF
0x01BB FFFF
0x01BC 0FFF
0x01BC 17FF
0x01BC 18FF
0x01BF FFFF
0x01FF FFFF
0x09FF FFFF
0x0BFF FFFF
0x0FFF FFFF
0x1000 7FFF
0x1000 9FFF
0x1000 BFFF
0x1000 DFFF
0x1000 FFFF
0x110F FFFF
0x111F FFFF
0x117F FFFF
0x1180 FFFF
0x11E0 7FFF
0x11E0 FFFF
0x11F0 3FFF
0x11F0 FFFF
0x11F1 7FFF
0x1FFF FFFF
0x2000 7FFF
0x41FF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x8FFF FFFF
0xFFFF FFFF
SIZE
(Bytes)
ARM
8K
ARM RAM0 (Instruction)
8K
ARM RAM1 (Instruction)
8K
ARM ROM (Instruction)
8K
Reserved
8K
ARM RAM0 (Data)
8K
ARM RAM1 (Data)
8K
ARM ROM (Data)
8K
960K
1M
6M
64K
6112K
32K
Reserved
976K
48K
32K
9120K
3840K
4K
ARM ETB Memory
2K
ARM ETB Registers
256
ARM IceCrusher
255744 Reserved
4M
CFG Bus Peripherals
128M
EMIFA (Code and Data)
32M
Reserved
64M
VLYNQ (Remote)
32K
8K
8K
Reserved
8K
8K
17344K
1M
VICP
6M
Reserved
64K
L2 RAM/Cache
6112K
Reserved
32K
L1P Cache
976K
Reserved
48K
L1D RAM
32K
L1D RAM/Cache
241M-32K Reserved
32K
DDR2 Control Regs
544M-32k Reserved
224M
Reserved
768M
Reserved
256M
DDR2
1792M
Reserved
C64x+
Reserved
VICP
Reserved
L2 RAM/Cache
Reserved
L1P Cache
Reserved
L1D RAM
L1D Cache
Reserved
CFG Space
CFG Bus Peripherals
EMIFA (Data)
Reserved
ARM RAM0
ARM RAM1
ARM ROM
Reserved
VICP
Reserved
L2 RAM/Cache
Reserved
L1P Cache
Reserved
L1D RAM
L1D RAM/Cache
Reserved
DDR2 Control Regs
Reserved
EMIFA/VLYNQ Shadow
Reserved
DDR2
Reserved
EDMA/
PERIPHERAL
Reserved
ARM RAM0
ARM RAM1
ARM ROM
Reserved
CFG Bus Peripherals
EMIFA (Data)
Reserved
VLYNQ (Remote)
Reserved
ARM RAM0
ARM RAM1
ARM ROM
Reserved
VICP
Reserved
L2 RAM/Cache
Reserved
L1P Cache
Reserved
L1D RAM
L1D RAM/Cache
Reserved
DDR2 Control Regs
Reserved
EMIFA/VLYNQ Shadow
Reserved
DDR2
Reserved
HPI
Reserved
ARM RAM0
ARM RAM1
ARM ROM
VPSS
Reserved
Reserved
DDR2 Control Regs
Reserved
DDR2
Reserved
(1) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000
through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be
used by C64x+ for both code execution and data accesses.
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