GC5318 Datasheet, PDF (7/45 Pages) Texas Instruments – HIGH-DENSITY DIGITAL UPCONVERTER

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GC5318
HIGH-DENSITY DIGITAL UPCONVERTER
SLWS187 – JULY 2006
Each DUC block has two serial input data pins; see Figure 2-3. These pins are used to transfer I/Q
baseband data into the DUC channel for interpolation, filtering, and tuning to a carrier frequency. The
channel configuration of the block determines how these pins are used.
When the block is configured for two CDMA channels, one pin (txin_X_a) accepts serial data for signal A;
the other pin (txin_X_b) for signal B. Input I and Q data, programmable up to 18 bits, are multiplexed over
the serial input pin starting with the most significant I bit. The maximum input bit rate is txclk. The interface
can be programmed to accept up to 32 bits, but only the upper 18 bits will be used as input signal data.
The most significant bit is sent first.
When the block is configured for a single UMTS channel, the txin_a is for I data, and txin_b carries the Q
data.
The four-pin mode is less common. It employs another two pins from the adjacent (2k + 1) DUC,
sacrificing the use of that DUC ito allow reduced data rate on the serial pins. The I data (Imsb, Imsb-1) are
carried on txin _(2k) _a and txin _(2k)_b, while the Q data (Qmsb Qmsb-1) are carried on txin _(2k + 1) _a
and txin _(2k + 1) _b.
Each pair of blocks (2k and 2k + 1) shares the clock division, frame delay, sync generation, and a frame
strobe output pin.
A programmable clock divider circuit can be used to specify the serial bit rate with respect to txclk. The
divider is programmed as txclk / (1+serp_trans_clkdiv). The clock divider circuit is synchronized using a
general sync block discussed in another section of this document.
The frame sync interval can be programmed from 1 to 127 bit-periods (which are divided clocks).
The number of bits in a word is set as (serp_tran_bits+1).
The frame strobe is an output from the GC5318 that indicates when the msb is expected. The frame
strobe can be programmed to arrive from 0 to 3 bit clocks ahead of when the msb is expected via the
serp_tran_fsdel parameter. The source must transmit all of its data before the next frame strobe is
generated. Use of the frame strobe is optional. The sync (ssel_serial) parameter determines when the
msb is expected.
The parameter chosen must satisfy the following constraints:
• serp_tran_fsinv × (serp_tran_clkdiv+1) = 4 × (cic_interp_decim+1)
• serp_tran_fsinv ≥ (serp_tran_bits+1)2 for CDMA mode
• serp_tran_fsinv ≥ (serp_tran_bits+1) for UMTS mode
• serp_tran_fsinv ≥ (serp_tran_bits+1)0.5 for four-pin mode
NOTE
For half-rate data (when serp_tran_clkdiv = 1), the MSB of the input data stream is
captured on the fourth rising edge of txclk, after txsync occurs. For full-rate data (when
serp_tran_clkdiv = 0), the MSB of the input data stream is captured on the third rising
edge of txclk, after txsync occurs.
See Figure 2-4 for a diagram of the serial transmit input timing.
GC5318 Operation
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