GC5318 Datasheet, PDF (36/45 Pages) Texas Instruments – HIGH-DENSITY DIGITAL UPCONVERTER

GC5318
HIGH-DENSITY DIGITAL UPCONVERTER
SLWS187 – JULY 2006
www.ti.com
Variable Name
phase_add_a_lsb
phase_add_a_msb
phase_add_b_lsb
phase_add_b_msb
phase_offset_a
phase_offset_b
dither_ena
test_bits_1
pmeter_sync_disable
ddc_duc_ena
mixer_gain
mpu_ram_read
sumchn_sel_b
sumchn_sel_a
tst_sel_block
serp_tran_bits
serp_tran_fsdel
serp_tran_4pin
serp_tran_fsinvl
serp_tran_clkdiv
ssel_pilot
Type Page
C 0100
C 0100
C 0100
C 0100
D 0100
D 0100
D 0100
E 0100
D 0100
U 0100
U 0100
E 0100
U 0100
U 0100
E 0100
U 0100
D 0100
D 0100
U 0100
U 0100
U 0120
Address
(HEX)
13
14
15
16
17
18
19
19
19
19
19
19
19
19
1A
1B
1B
1B
1B
1C
0B
LSB
Position
0
0
0
0
0
0
15
13
12
11
9
8
4
0
0
11
8
7
0
0
4
Bit
Width
16
16
16
16
16
16
1
2
1
1
1
1
4
4
6
5
2
1
7
4
3
Default
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
17
1
0
50
1
0
Description
This 32 bit word is used to control the frequency of the
NCO. Derived from the keyword freqa by cmd5318. (for
CDMA channel A or UMTS channel). Lower 16 bits.
Upper 16 bits of the above 32-bit word.
This 32-bit word is used to control the frequency of the
NCO. Derived from the keyword freqb by cmd5318. (for
CDMA channel B). Lower 16 bits.
Upper 16 bits of the above 32-bit word.
This is the fixed phase offset added to the output of the
frequency accumulator for sinusoid generation in the NCO.
(UMTS mode and A channel in CDMA mode)
This is the fixed phase offset added to the output of the
frequency accumulator for sinusoid generation in the NCO
for CDMA B channel.
This bit controls whether or not dither is turned on(1) or
off(0).
TEST BITS. Set to 0 for normal operation.
Turns off the sync to the channel power meter. This can be
used to individually turn off syncs to a channels power
meter, while still having syncs to other power meters on the
chip.
When set this turns on the DUC.
Adds a fixed –6 dB of gain to the mixer output(before round
and limiting) when asserted. Else adds –12-dB gain when
deasserted.
(TESTING PURPOSES) Allows the coefficient RAMs in the
PFIR/CFIR to be read out the mpu data bus. This cannot
be done during normal operation and must be done when
the state of the output data is not important. THIS BIT
MUST BE SET ONLY DURING THE READ OPERATION.
This word controls the second set of additions for the
CDMA B signal in the sumchn output. The selection bits
are not mutually exclusive.
This word controls the first set of additions for the CDMA A
signal (or UMTS signal) in the sumchn output. The
selection bits are not mutually exclusive.
(TESTING PURPOSES) This is the selection of which
signal comes out the test bus. When a constant `0' is
selected this also reduces power by preventing the data at
the input of the test block from changing. Howeve,rit does
not stop the clock.
Number of input bits per sample-1; for 18 bits, this is set to
{10001}.
Delay between frame sync output and MSB of serial data
{3, 2, 1, 0}.
Selects 2-pin mode when cleared and 4-pin mode when
set.
Transmit serial interface frame sync interval in bit clocks.
Transmit serial interface clock divider rate-1; 0 is full rate,
and 15 divides the clock by 16. For example, to run the
serial interface at 1/4 the transmit clock, set
serp_tran_clkdiv(3:0) = 0011.
Selects the sync source for the DUC pilot code generator.
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GC5318 Programming