GC5318 Datasheet, PDF (43/45 Pages) Texas Instruments – HIGH-DENSITY DIGITAL UPCONVERTER

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GC5318
HIGH-DENSITY DIGITAL UPCONVERTER
SLWS187 – JULY 2006
6.6 AC Characteristics
PARAMETER ⁽¹⁾
Clock frequency ( txclk) in selected modes⁽²⁾⁽³⁾
F_CK
Clock frequency ( txclk) unrestricted⁽²⁾
t_TXCKL
t_TXCKH
t_r, t_f
t_su(TX)
t_h(TX)
t_d(TX)
t_OH(TX)
F_JCK
t_JCKL
t_JCKH
t_su(J)
t_h(J)
t_d(J)
t_su(UPA)
t_h(UPA)
t_su(UPD)
t_h(UPD)
t_h
t_d(UP)
t_UPCKL
t_UPCKH
Clock low period (below V_IL) (txclk)⁽²⁾
Clock high period (above V_IH) (txclk)⁽²⁾
Clock rise and fall times (V_IL to V_IH) (txclk)⁽⁴⁾
Input setup (txin_[0–11]_[a–b], tx_sync[a–d]) before txclk rises⁽²⁾
Input hold (txin_[0–11]_[a–b], tx_sync[a–d]) after txclk rises⁽²⁾
Data output delay (tx_sync_out_[0–5], tx_iflag, txout_[a–d]_[0–17]) after txclk rises⁽²⁾
Data output hold (tx_sync_out_[0–5], tx_iflag, txout_[a–d]_[0–17]) after txclk rises⁽²⁾
JTAG clock frequency (tck)⁽²⁾
JTAG clock low period (below V_IL) (tck)⁽²⁾
JTAG clock high period (above V_IH) (tck)⁽²⁾
JTAG input (tdi or tms) setup before tck goes high⁽²⁾
JTAG input (tdi or tms) hold time after tck goes high⁽²⁾
JTAG output (tdo) delay from falling edge of tck⁽²⁾
Microprocessor address setup to falling edge of controls⁽²⁾
Microprocessor address hold from rising edge of controls⁽²⁾
Microprocessor data setup to rising edge of controls during writes⁽²⁾
Microprocessor data hold from rising edge of controls during writes⁽²⁾
Microprocessor data output hold from rising edge of controls (read)(⁽⁵⁾
Microprocessor data output delay from falling edge of controls (read)⁽²⁾
Microprocessor control low time⁽²⁾
Microprocessor control high time⁽²⁾
MIN MAX UNIT
125
MHz
80
3
ns
3
ns
2 ns
2.2
ns
1.1
ns
6.5 ns
1.5
ns
40 MHz
8
ns
8
ns
2
ns
9
ns
6 ns
2.5
ns
2
ns
12
ns
2.6
ns
0
ns
36 ns
30
ns
8.4
ns
(1) Timing is measured from the respective clock at V_PAD/2 to input or output at V_PAD/2. Output loading is a 50-Ω transmission line whose
delay is calibrated out.
(2) Each part is tested at +90°C case temperature for the given specification. Lots are sample tested at –40°C.
(3) Excluding tx_sync_out, tx_sync_out_[1–5].
(4) Recommended practice.
(5) Controlled by design and process and not directly tested. Verified on initial part evaluation.
Specifications
43